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12+-+Case+Studies - CS 4290/6290 Processor Case Studies...

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CS 4290/6290 Processor Case Studies 
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic Basis for Centrinos, Core, Core 2 (We’ll also look at P4, Core 2, Core i7 after this.) 2
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic (commit) (issue/alloc) RS: 20 entries, unified ROB: 40 entries 3
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 11 11 12 12 13 13 14 14 15 15 16 16 17 17 20 20 21 21 22 22 Next IP Next IP I-Cache ILD ILD Rotate Dec1 Dec2 Dec2 Br Dec RS Write RS Write RAT RAT IDQ In-order FE In-order FE 31 32 33 33 81 82 .. .. .. .. 83 Exec2 Exec n Exec n Multi-cycle Multi-cycle pipeline pipeline 31 31 32 32 33 33 81 81 82 82 42 43 83 83 AGU AGU DCache1 DCache2 DCache2 Non-blocking Non-blocking memory memory pipeline pipeline 31 32 33 33 82 83 RS schd RS Disp RS Disp Exec / WB Single-cycle pipeline pipeline 83: Data WB 83: Data WB 82: Int WB 81: Mem/FP WB FE in-order boundary FE in-order boundary Retirement in-order boundary Retirement in-order boundary 91 92 93 Ret ptr wr Ret ptr wr Ret ROB rd Ret ROB rd RRF wr RRF wr …….. RS RS Scheduling Scheduling Delay Delay ROB ROB Retirement Retirement Delay Delay MOB MOB Scheduling Scheduling Delay Delay 31 32 33 81 81 82 82 42 43 83 83 AGU AGU MOB MOB blk blk MOB wr 40 40 41 41 42 43 MOB disp DCache DCache 1 Dcache 2 Mob wakeup Blocking Blocking memory memory pipeline pipeline 4
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic FE 1 OOO 1 Normal execution: speculatively fetch and execute instructions FE 1 OOO 1 OOO core detects misprediction, flush FE and start refetching FE 2 OOO 1 New insts fetched, but OOO core still contains wrong-path uops FE 2 FE 2 OOO 1 OOO core has drained, retire bad branch and flush rest of OOO core FE 2 FE 2 OOO 2 Normal execution: speculatively fetch and execute instructions 5
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic Tag Target Hist 2-bit ctrs BTB PC = Use dynamic predictor hit? Use static predictor: Stall until decode miss? PC-relative? Conditional? Backwards? Backwards? Return? Return? No No No No No No Yes Yes Yes Yes Yes Yes Taken Taken Taken Taken Taken Indirect jump Not Taken Not Taken 6
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic CISC RISC Simple x86 instructions map to single uop Ex. INC, ADD (r-r), XOR, MOV (r-r, load) Moderately complex insts map to a few uops Ex. Store STA/STD ADD (r-m) LOAD/ADD ADD (m-r) LOAD/ADD/STA/STD More complex make use of UROM PUSHA STA/STD/ADD, STA/STD/ADD, … 7
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 4-1-1 limitation Decode up to three instructions per cycle Three decoders, but asymmetric Only first decoder can handle moderately complex insts (those that can be encoded with up to 4 uops) If need more than 4 uops, go to UROM A: 4-2-2-2 B: 4-2-2 C: 4-1-1 D: 4-2 E: 4-1 8
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic
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