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13+-+Compiler+ILP - CS 4290/6290 Compiler ILP Techniques...

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CS 4290/6290 Compiler ILP Techniques
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Hard-to-predict branches Control hazard much worse than data hazard Convert control dependences into data dependences? Limited ILP exposed to HW Dependence chains limit ILP in general Shorten dependence chains? Looks at only so many instructions (ROB, RS limits) Move dependent instructions farther apart? CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 2
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if ( random( ) & 1 ) a++; else b++; No predictor can predict this accurately Remember, we want >90% or better But can’t even get 60% on this code Some non-random branches also very difficult Especially for simpler (cheaper, faster) predictors CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 3
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Observation: if-then-else code often very short Don’t try to guess where branch going! Do both sides, then keep only the work we want! How to keep only the results we want? Need conditional instructions Write result only if some condition true CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 4
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic CMOV R1, R2, R3 Actually a 4-operand instruction… R1 = R3 ? R2 : R1 If you rename this… P17 = P26 ? P4 : P8 There are four registers, not three! There are four registers, not three! OOO hardware more complicated OOO hardware more complicated (RS needs three sources) (RS needs three sources) if(cond) a++; else b++; BEQZ R1,else ADDI R2,R2,1 B end else: ADDI R3,R3,1 end: ADDI R4,R2,1 ADDI R5,R3,1 CMOV R2,R4,R1 CMOV R3,R5,R1 Hard to predict! Hard to predict! No branches! No branches! Problem: Uses more registers, need a CMOV for each value Problem: Uses more registers, need a CMOV for each value 5
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic “Full Predication” Every instruction can be predicated Often with separate predicate registers And separate instructions to set predicates Need extra bits in every instruction Must specify predicate Four-operand instrs (2 src, 1 predicate, 1 dst) Must change the ISA Used in Intel Itanium, but not x86 Also used in TriMedia, SHARC, etc. 6
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 7 if(cond) a++; else b++; BEQZ R1,else ADDI R2,R2,1 B end else: ADDI R3,R3,1 end: CMP.EQZ P1,P2,R1 (P1) ADDI R2,R2,1 (P2) ADDI R3,R3,1 Hard to predict! Hard to predict! P1= (R1==0) P2= (R1!=0) IF P1 THEN ADDI R2,R2,1 IF P3 THEN ADDI R3,R3,1
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic When predicate is false, instruction must appear as a NOP! (pF) DIV R1 = R2 / R0 (pF) DIV R1 = R2 / R0 (pF) LOAD R1 = 0[R0] (pF) LOAD R1 = 0[R0] (pF) LOAD R1 = 0[R5] (pF) LOAD R1 = 0[R5] DBZ cannot be exposed NULL reference cannot be exposed Page fault cannot be exposed 8
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic If-conversion: use predication to transform if-then-else into branch-free code Potential performance improvement Convert hard-to-predict control dependences into regular data dependences Avoid costly branch mispredictions
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