17+-+Synchronization

17+-+Synchronization - CS 4290/6290 Synchronization and...

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CS 4290/6290 Synchronization and Memory Consistency
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All microarchitecture performance gains up to this point were “free” in that no user intervention required beyond buying the new processor/system recompilation/rewriting could provide even more benefit, but you get some even if you do nothing Multi-processing pushes the problem of finding the parallelism to above the ISA interface CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 2
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Shared counter/sum update example Use a mutex variable for mutual exclusion Only one processor can own the mutex • Many processors may call lock(), but only one will succeed (others block) • The winner updates the shared sum, then calls unlock() to release the mutex • Now one of the others gets it, etc. But how do we implement a mutex? As a shared variable (1 – owned, 0 –free) CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 3
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Releasing a mutex is easy Just set it to 0 Acquiring a mutex is not so easy Easy to spin waiting for it to become 0 But when it does, others will see it, too Need a way to atomically see that the mutex is 0 and set it to 1 CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 4
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Atomic exchange instruction E.g., EXCH R1,78(R2) will swap content of register R1 and mem location at address 78+R2 To acquire a mutex, 1 in R1 and EXCH • Then look at R1 and see whether mutex acquired • If R1 is 1, mutex was owned by somebody else and we will need to try again later • If R1 is 0, mutex was free and we set it to 1, which means we have acquired the mutex Other atomic read-and-update instructions E.g., Test-and-Set CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 5
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Atomic instructions OK, but specialized Idea: provide a pair of linked instructions A load-linked (LL) instruction Like a normal load, but also remembers the address in a special “link” register A store-conditional (SC) instruction Like a normal store, but fails if its address is not the same as that in the link register Returns 1 if successful, 0 on failure Writes by other processors snooped If address matches link address, clear link register CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 6
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swap: mov R3, R4 ll R2,0(R1) sc R3,0(R1) beqz R3,swap mov R4,R2 Atomic Exchange upd: ll R2,0(R1) add R3,R2,R4 sc R3,0(R1) beqz R3,upd Atomic Add to Shared Variable mov R3,1 ll R2,0(R1) sc R3,0(R1) bnez beqz Swap R4 w/ 0(R1)
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17+-+Synchronization - CS 4290/6290 Synchronization and...

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