18+-+Many-Core

18+-+Many-Core - CS 4290/6290 Manycore Processors One...

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CS 4290/6290 Many-core Processors
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic One approach: add sockets to your MOBO minimal changes to existing CPUs power delivery, heat removal and I/O not too bad since each chip has own set of pins and cooling CPU 0 CPU 1 CPU 2 CPU 3 Pictures found from google images 2
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic Simple SMP on the same chip Intel “Smithfield” Block Diagram AMD Dual-Core Athlon FX Pictures found from google images 3
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CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic Resources can be shared between CPUs ex. IBM Power 5 CPU 0 CPU 1 L2 cache shared between both CPUs (no need to keep two copies coherent) L3 cache is also shared (only tags are on-chip; data is off-chip) 4
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Moore’s Law - core count doubles every 2 years Off-chip bandwidth becomes a problem Need large on-chip cache to reduce off-chip demand This large on-chip cache should be shared • Prevent replication (multiple cores access same data) • Prevent underutilization (some code needs more cache) Large on-chip cache becomes bottleneck Must service all L1 misses from 10s of cores Solution 1: have L2 cache per-core, share large L3 • OK, but L3 smaller (need space for L2s) Solution 2: distributed cache CS 4290/6290 – Spring 2009 – Prof. Milos Prvulovic 5
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“Tile”: core, its L1, and a part of L2 The L2 is composed of all L2 tiles together Kind of like node in DSM Miss in L1 – need to find data in L2 Which tile can have it? Static: block’s address determines tile number Usually part of “index”: lower bits = tile, upper bits = index within tile Dynamic: block can be in any tile • How do we find it? Home tile!
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18+-+Many-Core - CS 4290/6290 Manycore Processors One...

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