CS6290Final

CS6290Final - Name____________________________________ GT

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Unformatted text preview: Name____________________________________ GT username__________________ 1 of 14 CS 6290: High-Performance Computer Architecture Spring 2009 Final Exam This exam is to be done by each student individually, with no collaboration or input from other students. The answers to the exam should be submitted in T-Square before the due time. T-Square will not accept late submissions for the Final Exam assignment (there will be no grace period). The penalty for submitting late will be 10 points plus 1 point per minute (rounded up) for up to 90 minutes. To submit late, use the Late Final Exam assignment in T-Square. For example, if you submit a Late Final Exam at 02:00:01pm or at 02:00:59pm Atlanta time, there will be an 11-point penalty (10 points for being late plus 1 point for being up to 1 minute late). Problem Points Earned Points 1 20 2 10 3 10 4 20 5 20 6 20 Total 100 Name____________________________________ GT username__________________ 2 of 14 Problem 1. [20 points] Tomasulos Algorithm This problem is about a processor that uses Tomasulos algorithm (no ROB), with a total of 3 reservation stations. Any instruction can use any reservation station. The processor is 1-wide. We do not know the execution latencies of particular instructions. We also do not know which other instructions have already completed execution or which instructions still remain to be issued. The current state of reservation stations is: Reservation Stations Name Busy? Op V j V k Q j Q k RS0 Yes MUL RS1 RS2 RS1 Yes ADD 3 RS2 RS2 Yes SUB 10 7 A) When the MUL instruction broadcasts its result on the CDB, what data value and tag (name) will it put on the CDB? B) Can we say for sure that next broadcast on the CDB will be for the result of the SUB instruction that is in RS2 (and not the ADD, the MUL, or some other instruction)? Explain your answer. Note: If we can say for sure, explain why we can be sure. If we cannot say for sure, give an example that shows how another instruction can broadcast its result before the SUB does. Name____________________________________ GT username__________________ 3 of 14 C) Can we say for sure that the ADD in RS1 will be the second instruction to broadcast its result? In other words, can we be sure that the processor will only broadcast one result on the CDB between now and the time the ADD instruction in RS1 broadcasts its result? Explain your answer. Note: If we can say for sure, explain why we can be sure. If we cannot say for sure, give an example that shows how another instruction can be the second instruction to broadcast its result. D) Can we say for sure that the MUL instruction in RS0 was the very last instruction issued by the processor until now? In other words, can we be sure that that the processor has issued no instructions since the MUL instruction was issued?...
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CS6290Final - Name____________________________________ GT

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