HW3Solution - Homework 3 Prof. Milos Prvulovic CS 4290/6290...

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Homework 3 Prof. Milos Prvulovic CS 4290/6290 - Spring 2009 Handed Out: Feb 26 th 2009 Due: Mar 5 th 2009 This homework counts as 5% of the overall class grade. Submit your answers in T-Square as a single PDF document. You can either hand-write your answers and scan them into a PDF document, or write your answers in a text processor (e.g. LaTeX) and generate a PDF document from that (e.g. pdflatex). No printed submissions will be accepted. In case you hand-write your answers, keep in mind that illegible answers will be considered to be wrong answers. 1. A processor is using a 4KByte 4-way set-associative L1 data cache with a 64-byte block size. This cache is virtually indexed and physically tagged, and the processor’s virtual address size is 64 bits but the physical address is only 48 bits. a) What is the smallest page size that can be used without running into aliasing problems in this L1 cache? The cache is virtually indexed, so to avoid aliasing the cache index bits must all come from the page offset. There are 4096 bytes in the cache and the block size is 64 bytes, so we have 64 cache lines (blocks). The cache is 4-way set-associative so we have 16 sets. The block offset is the least significant 6 bits (64-byte block), and the next 4 bits are the index, so the page size must be 1KB (2^10 bytes) or more to avoid aliasing. b) How many sets are there in this cache and how many lines are there in each set? There are 16 sets, each with 4 blocks. c) The cache keeps a tag for each line to compare it with the tag of the requested address. How many bits are needed in this entire cache to store all these tags? The tag is whatever remains of the physical address (cache is physically tagged) when we remove block offset and index bits, so we have a 38-bit (48-6-4) tag with each cache line. The number of lines in the cache is 64, so we need 2432 (38*64) bits to hold all of the tags. d) If this is a write-back cache with a FIFO replacement policy, which other information must be kept (besides data and tags) for correct operation of this cache? How many bits (in total for the entire cache) are needed to keep this information. We need one FIFO counter per set. The size of the counter is 2 bits (to point to one of the four lines in a set) and the number of sets is 16, for a total of 32 bits for FIFO counters. We also need Valid bits, one bit per line for a total of 64 bits. There is also a Dirty bit with each line so we have another 64 bits. Overall, we need a total of 150 (32+64+64) bits in addition to the tag and data bits. 2.
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This note was uploaded on 04/12/2010 for the course CS 6290 taught by Professor Staff during the Spring '08 term at Georgia Institute of Technology.

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HW3Solution - Homework 3 Prof. Milos Prvulovic CS 4290/6290...

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