HW4Solution - Homework 4 Prof. Milos Prvulovic CS 4290/6290...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Homework 4 Prof. Milos Prvulovic CS 4290/6290 - Spring 2009 Handed Out: March 26 th 2009 Due: April 7 th 2009 This homework has 3 regular problems and counts as 5% of the overall class grade. It also has an extra-credit question that can add 50 points to your score and thus improve your overall class grade by up to 2.5%. As always, submit your answers in T-Square as a single PDF document. You can either hand-write your answers and scan them into a PDF document, or write your answers in a text processor (e.g. LaTeX) and generate a PDF document from that (e.g. pdflatex). No printed submissions will be accepted. In case you hand-write your answers, keep in mind that illegible answers will be considered to be wrong answers. 1. [40 points] A simple shared-memory cache-coherent machine has four processors, no virtual-to-physical translation and 16-bit (physical) addresses. There is one L1 data cache per processor and there is no L2 cache. Each L1 cache is direct-mapped with four 64-byte blocks (the size of each cache is 256 bytes), and they are kept coherent using the MESI coherence protocol. The initial state of each cache is as follows (tags are shown in hexadecimal notation): P0 P1 P2 P3 State Tag State Tag State Tag State Tag I 0F S 0F S 01 S 01 M 01 E 02 M 03 E 04 I 0F I 0F E 0F I 0F M 00 E 02 S 04 I 06 What happens if the following memory access is executed next. In particular, specify whether the access is a cache hit or a miss, is there a write-back, is there a broadcast on the shared bus as a result of this access, what (if anything) happens in each of the other caches as a result of the bus broadcast, where the data comes from (if not already in the cache), and what the new state of the block is in the requestor’s cache and why. For each part of this problem, start with the state of the cache shown above, not with the state left by prior questions. For example, in part b) do not assume that the access in part a) has already happened. a) P0 writes a word to address 00FC Offset is 3C, index is 3, tag is 00. This block is already in the cache in the M state, so the access is a hit [2 points] and the state of the cache is unmodified [2 points]. [Zero points here if answer says there is a broadcast or other caches involved] b) P1 reads a word from address 0F8C Offset is 0C, index is 2, tag is 0F. The (one) cache line in set 2 is invalid, so this is a miss [1 point] and there is no write-back. P1’s cache does broadcast a request for this block on the bus [1 point]. All other caches snoop this broadcast and P2’s cache finds that it has this block in an E state, so it changes its own state to S [1 point] and asserts
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
the bus Shared signal but lets the memory respond (or P2’s cache could respond with the data). P1’s cache gets the data and sets the state to S [1 point]. [-2 points if P0 or P3 caches change state, -4 if one of them responds with data]
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 14

HW4Solution - Homework 4 Prof. Milos Prvulovic CS 4290/6290...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online