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Unformatted text preview: EE116c/CS151b Quiz 2 Allotted Time: 1 hour Total Points: 50 One double‐sided handwritten sheet + MIPS cheatsheet (from book) + calculator allowed Q1. 30points Multicycle datapath can have a small speed overhead due to the extra registers (recall the “setup time” of a flipflop). For some multicycle CPU, the clock period is 100ps out of which 25ps is the “setup time”. Assume that all steps of the MIPS multicycle CPU are perfectly delay‐balanced. a) What would be the clock period of the fastest possible single‐cycle implementation of this CPU ? Answer: 400ps. At least, CPI in multicycle datapath is 5 in order to perform all kinds of instructions, so the clock period of the fastest possible single‐cycle needs 5*(100‐25) = 375ps, plus 25ps for the initial “setup time”, which is 400ps totally. b) Write a sequence of 4 instructions which will execute faster on multi‐cycle machine. Answer: j L1 (300) L1: add $t1, $t2, $t3 (400) sw $t1, 16($t4) (400) j L2 (300) The run time of the sequence of the 4 instructions is 1400ps. However, if it’s implemented by singlecycle datapath, it will need 4*375=1500ps to perform. c) Write a sequence of 4 instructions which will execute faster on the single cycle machine. Answer: lw $t1, 8($t2) (500) add $t3, $t1, $t4 (400) sll $t5, $t3,1 (400) sw $t5, 0($t6) (400) The run time of the sequence of the 4 instructions is 1700ps. However, if it’s implemented by singlecycle datapath, it will just need 4*375=1500ps to perform. Q2. 10 points Can you infinitely pipeline a processor ? I.e. does the throughput keep on increasing if one keeps on increasing the number of pipeline stages ? Why or why not ? Answer: You can actually infinitely pipeline a system but for two main issues: 1. Pipeline registers have overhead. At certain point, pipeline register overhead will exceed the throughput benefit 2. After certain point, you cannot subdivide computations. E.g., if the computation is already just one gate long. Q3. 10 points Suppose that a CPU can be enhanced so it can execute floating point instructions x times faster than a given implementation. Suppose that the relative frequency of floating point instructions in an application program is 50%, how high need x to be in order to achieve an overall speedup of 1.25? (Suppose in the reference implementation all instructions have same CPI. And the CPU is a multi‐cycle one) Answer: 50% * CPI + 50% * CPI 5 = 1.25 , x= 50% * CPI 3 + 50% * CPI x ...
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This note was uploaded on 04/12/2010 for the course EE M116C taught by Professor Puneetgupta during the Fall '08 term at UCLA.
 Fall '08
 PUNEETGUPTA

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