370L10 - EECS/CS 370 Basic Processor Design Lecture 10 PC...

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Unformatted text preview: EECS/CS 370 Basic Processor Design Lecture 10 PC Instruction memory Register file Data memory Control ROM M U X M U X M U X M U X Sign extend + 1 + A L U 3x8 decoder R/W En En Examining the components of our LC2K1 datapath Register file A L U Register File Design D G Q Enable Write data decoder write reg decoder decoder read reg 1 read reg 2 read data 1 read data 2 2 read + 1 write register file is bigger than a 1 read or 1 write memory cell, why? 1 1 1 ALU A L U Input A Input B result operation Input A Full Adder Circuit Input B result operation Half and Full adder Half Adder A B S C A B 1 1 1 1 1 1 S 1 C Full Adder A B C S 1 8-bit Ripple Carry Adder Full adder C A 7 B 7 A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A 1 B 1 A B Full adder Full adder Full adder Full adder Full adder Full adder Full adder S 7 S 2 S 1 S S 6 S 5 S 4 S 3 Carry Unfortunately this has a very large propagation time for 32 or 64 bit adds 8-bit Carry Look-ahead Adder A 7 B 7 A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A 1...
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This note was uploaded on 04/13/2010 for the course CS 212 taught by Professor Daruwala during the Spring '10 term at Punjab Engineering College.

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370L10 - EECS/CS 370 Basic Processor Design Lecture 10 PC...

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