370L11 - EECS/CS 370 Basic Processor Design Lecture 11...

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EECS/CS 370 Basic Processor Design Lecture 11
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What’s wrong with single cycle? All instructions run at the speed of the slowest instruction. Adding a long instruction can hurt performance What if you wanted to include multiply? You can not reuse any parts of the processor We have 3 different adders to calculate PC+1, PC+1+offset and the ALU No profit in making the common case fast Since every instruction runs at the slowest instruction speed This is particularly important for loads as we will see later
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What’s wrong with single cycle? 1ns – Register read/write time 2ns – ALU/adder 2ns – memory access 0ns – MUX, PC access, sign extend, ROM add: 2ns + 1ns + 2ns + 1ns = 6ns beq: 2ns + 1ns + 2ns = 5ns sw: 2ns + 1ns + 2ns + 2ns = 7ns lw: 2ns + 1ns + 2ns + 2ns + 1ns = 8ns Get read ALU mem write Instr reg operation reg
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Computing execution time Assume: 100 instructions executed 25% of instructions are loads, 10% of instructions are stores, 45% of instructions are adds, and 20% of instructions are branches. Single-cycle execution: 100 * 8ns = 800 ns Optimal execution: 25*8ns + 10*7ns + 45*6ns + 20*5ns = 640 ns
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Multiple-cycle Execution Each instruction takes multiple cycles to execute Cycle time is reduced Slower instructions take more cycles Can reuse datapath elements each cycle What is needed to make this work? Since you are re-using elements for different purposes, you need
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This note was uploaded on 04/13/2010 for the course CS 212 taught by Professor Daruwala during the Spring '10 term at Punjab Engineering College.

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370L11 - EECS/CS 370 Basic Processor Design Lecture 11...

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