370L12 - EECS/CS 370 Basic Processor Design Lecture 12...

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EECS/CS 370 Basic Processor Design Lecture 12
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PC Memory Register file M U X M U X M U X Sign extend A L U R/W En En M U X M U X 1 Instruction Reg Control Multi-cycle Datapath addr data En En
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Mapping instructions to the multi-cycle processor Add: 4 cycles Fetch, decode, ALU (add), register write Nand: 4 cycles Fetch, decode, ALU (nand), register write Lw: 5 cycles Fetch, decode, ALU (address calculation), memory read, register write Store: 4 cycles Fetch, decode, ALU (address calculation), memory write
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Mapping instructions to the multi-cycle processor Beq: 3 cycles if not taken Fetch, decode, compare Beq: 4 cycles if taken Fetch, decode, compare, branch target address calculation We can reduce this to 3 cycles by adding one register and another MUX, how?
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PC Memory Register file M U X M U X M U X Sign extend A L U R/W En En M U X M U X 1 Instruction Reg Control Multi-cycle Datapath with 4-cycle taken beq addr data En En
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Multi-cycle Datapath with 3-cycle beq t PC Memory Register file M U X M U X M U X Sign extend A L U R/W En En M U X M U X 1 Instruction Reg Control addr data En En M U X En
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370L12 - EECS/CS 370 Basic Processor Design Lecture 12...

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