370L31 - EECS/CS 370 Input/Output Systems Lecture 31 1...

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1 EECS/CS 370 Input/Output Systems Lecture 31
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2 Computer Parts Input: Keyboard, mouse and Microphone CD ROM, DVD, Scanner Output: Printer Graphics screen and speakers Input/Output Disk drive, network, read/write CD
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3 Bus Design Synchronous Bus has clock Communication protocol is fixed to clock Cycle 1: Processor send address and read request to memory Cycle 2-25: Idle Cycle 26-29:data transferred from memory Fast since protocol timing is fixed
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4 Bus Design Asynchronous Bus does not have a clock Has extra control lines to say when ready Processor raises request line (req line) Processor send data Device acknowledges request (ack line) Both sides have finite state machine Control lines identify state transitions
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5 Bus Design Must decide on: Width Wider generally means more expensive (especially for I/O buses with external cables Speed Faster generally means shorter lengths Contention policy or arbitration If more than one component can initiate a bus transaction, we need to manage contention.
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6 Arbitration Must meet two conflicting design goals: Priority : service highest priority device first Fairness : avoid “ starving ” some device Different Bus contention policies: Daisy chained, centralized, decentralized and collision detect.
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Daisy Chained Devices One request bus line – any device can raise it (wired-or line) One grant bus line – sent to highest priority device first If this device raise a request, it take control of the bus. If this device did not raise a request, grant bus line is passed to next highest device, etc. Advantage : 2 control lines for arbitration, easily expanded. Disadvantages
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370L31 - EECS/CS 370 Input/Output Systems Lecture 31 1...

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