370L26 - EECS/CS 370 Cache Interactions Short Lecture How...

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EECS/CS 370 Cache Interactions
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Short Lecture How are caches integrated into a pipelined implementation? Replace instruction memory with Icache. Replace data memory with Dcache. Issues Memory access now have variable latency. Both caches may miss at the same time.
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PC ICache Register file M U X A L U M U X 1 Dcache + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X add 11 7 21 lw nand 75 nand 1 2 5 7 10 11 14 0 R2 R3 R4 R5 R1 R6 R0 R7 regA regB 4 5 data 3 Pipeline with caches To mem To mem
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PC ICache Register file M U X A L U M U X 1 Dcache + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X add 11 7 21 lw noop nand 1 2 5 7 10 11 75 14 0 R2 R3 R4 R5 R1 R6 R0 R7 regA regB 4 data 3 Pipeline with caches after miss To mem To mem
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PC ICache Register file M U X A L U M U X 1 Dcache + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB M U X nand 7 14 18 add lw 99 7 10 11 75 14 0 R2 R3 R4 R5 R1 R6 R0 R7 regA regB 3 4 data 5 Pipeline with caches after hit
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Blocking Caches on miss? What about out of order execution pipelines?
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This note was uploaded on 04/13/2010 for the course CSE 245 taught by Professor Dawan during the Spring '10 term at Punjab Engineering College.

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370L26 - EECS/CS 370 Cache Interactions Short Lecture How...

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