370L25 - EECS/CS 370 Memory Systems Associativity Lecture...

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EECS/CS 370 Memory Systems – Associativity Lecture 25
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Seven lectures on memory 1. Introduction to the memory systems 2. Basic cache design 3. Write-back and Write-through caches 1. Associativity 1. Cache interactions 2. Virtual Memory 3. Making VM faster: TLBs
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Associativity We designed a fully associative cache. Any memory location can be copied to any cache line. We check every cache tag to determine whether the data is in the cache. This approach can be too slow sometimes. Parallel tag searches are slower. Why?
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Direct mapped cache We can redesign the cache to eliminate the requirement for parallel tag lookups. Direct mapped caches partition memory into as many regions as there are cache lines. Each memory region has a single cache line in which data can be placed. You then only need to check a single tag – the one associated with the region the reference is located in.
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Mapping memory to cache 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tag data 78 120 71 173 21 28 200 225 tag line index block offset Address: 0 1 2 3 1 bit 2 bits 1 bit
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Direct-mapped cache 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 5 ] St R2 M[ 2 ] St R1 M[ 7 ] Ld R2 M[ 4 ] Cache Processor V d tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 0 Hits: 0 0 0 LRU
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Direct-mapped (REF 1) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 5 ] St R2 M[ 2 ] St R1 M[ 7 ] Ld R2 M[ 4 ] Cache Processor V d tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 0 Hits: 0 0 0
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Direct-mapped (REF 1) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 5 ] St R2 M[ 2 ] St R1 M[ 7 ] Ld R2 M[ 4 ] Cache Processor 0 78 29 V d tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 1 Hits: 0 0 1 0 29
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Direct-mapped (REF 2) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 5 ] St R2 M[ 2 ] St R1 M[ 7 ] Ld R2 M[ 4 ] Cache Processor 0 78 29 V d tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 1 Hits: 0 0 1 0 29
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Direct-mapped (REF 2) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 5 ] St R2 M[ 2 ] St R1 M[ 7 ] Ld R2 M[ 4 ] Cache Processor 1 71 150 V d tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 2 Hits: 0 0 1 0 29 150
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Direct-mapped (REF 3) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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370L25 - EECS/CS 370 Memory Systems Associativity Lecture...

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