370L24 - EECS/CS 370 Memory Systems Lecture 24 Seven...

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EECS/CS 370 Memory Systems Lecture 24
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Seven lectures on memory 1. Introduction to the memory systems 2. Basic cache design 1. Write-back and Write-through caches 1. Associativity 2. Cache interactions 3. Virtual Memory 4. Making VM faster: TLBs
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Questions to ask about a cache What is the block size? How many lines? How many bytes of data storage? How much overhead storage? What is the hit rate? What is the latency of an access? What is the replacement policy ? LRU? LFU? FIFO? Random?
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What about stores? Where should you write the result of a store? If that memory location is in the cache? Send it to the cache. Should we also send it to memory? ( write-through policy ) If it is not in the cache? Allocate the line (put it in the cache)? ( allocate-on-write policy ) Write it directly to memory without allocation?
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Handling stores (write-through) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[ 10 ] Cache Processor V tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 0 Hits: 0 0 0
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write-through (REF 1) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[ 10 ] Cache Processor V tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 0 Hits: 0 0 0
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write-through (REF 1) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[ 10 ] Cache Processor 0 V tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 1 Hits: 0 lru 1 0 29 78 29
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write-through (REF 2) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[ 10 ] Cache Processor 0 V tag data R0 R1 R2 R3 Memory 78 120 71 173 21 28 200 225 Misses: 1 Hits: 0 lru 1 0 29 78 29
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write-through (REF 2) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[ 10 ] Cache Processor 0 V tag data R0 R1 R2 R3 Memory 3 78 120 71 173 21 28 200 225 Misses: 2 Hits: 0 lru 1 1 29 78 29 162 173 173
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write-through (REF 3) 29 123 150 162 18 33 19 210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ld R1 M[ 1 ] Ld R2 M[ 7 ] St R2 M[ 0 ] St R1 M[ 5 ] Ld R2 M[
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This note was uploaded on 04/13/2010 for the course CSE 245 taught by Professor Dawan during the Spring '10 term at Punjab Engineering College.

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370L24 - EECS/CS 370 Memory Systems Lecture 24 Seven...

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