370L19 - EECS/CS 370 Pipeline Control Hazards Lecture 19...

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EECS/CS 370 Pipeline Control Hazards Lecture 19
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Next four lectures on pipelining Data hazards What are they? How do you detect them? How do you deal with them? Today: Control hazards Other issues: exceptions, performance, test case preparation Advanced topics
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PC Inst mem REG file M U X A L U M U X 1 Data memory + + M U X IF/ ID ID/ EX EX/ Mem Mem/ WB sign ext Control
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Pipeline function for BEQ Fetch: read instruction from memory Decode: read source operands from reg Execute: calculate target address and test for equality Memory: Send target to PC if test is equal Writeback: Nothing left to do
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Control Hazards beq 1 1 10 sub 3 4 5 time fetch decode execute memory writeback fetch decode execute beq sub
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Approaches to handling control hazards Avoidance Make sure there are no hazards in the code Detect and Stall Delay fetch until branch resolved. Speculate and Squash if wrong Go ahead and fetch more instruction in case it is correct, but stop them if they shouldn’t have been executed
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