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lecture3 - ELEC 303 ASIC Design with FPGA Introduction to...

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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 2-1 Introduction to Xilinx FPGA • FPGA Resources – logic blocks – input/output block – programmable interconnects • XC3000 Family – XC3000 IOB, CLB and interconnect – XC3000 examples » Application examples » Design examples • Self Reading Assignment – Page 1-20, XC3000 Data Sheet – Chapter 10-3, Randy Katz, Contemporary Logic Design, Prentice Hall, 1994 ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 2-2 Structure Programming Logic block Xilinx Symmetrical SRAM Look-up table Altera Hierarchical EPROM NAND Actel Row-based Anti-fuse Multiplexer FPGA Fundamentals • FPGA Structures – Symmetrical, Row-based, Sea-of-gates and Hierarchical Arrays • FPGA Programming Technologies – SRAM, Anti-fuse and EPROM/EEPROM • FPGA Logic Blocks – Look-up Table, Multiplexer, NAND Gates • Two Most Popular FPGAs – Xilinx www.xilinx.com – Altera www.altera.com – Actel www.actel.com
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 2-3 Introduction to Altera • Inventor of the EPLD in 1983 – the first product-term ELPD call “ Classic” – EPM7032 = “ PAL of the 90s” • Seven programmable logic families – Product term (EPLD) » Classic » MAX 5000 » MAX 7000 we used MAX7128 in our lab » MAX 9000 (not much difference with MAX7000) – Look-up table (FPGA) » FLASH logic » FLEX 8000 » FLEX 10K • Complex PLD is sometimes referred as Erasable PLD ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 2-4 CPLDs and FPGAs CPLD FPGA Architecture PAL/22V10-like Gate array-like Characteristics More Combinational More Registers +RAM Density Low-to-medium Medium-to-High (0.5-20K logic gates) (1K to 500K, 3.2M) Inventor Altera Xilinx MAX7000 XC4000 (XC9500 by Xilinx) (Flex10k by Altera)
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Ho-Chi Huang, Lecture Notes, No. 2-5 Introduction to Xilinx • The first FPGA was introduced by Xilinx in 1985 – XC2000 in 1989, XC3000 in 1991, XC4000 in 1993, … • CPLD – XC9500: Flash ISP, 600 - 7K gates • FPGA – XC4000: Industry’s largest FPGAs » XC4000E: 0.5 µ m, 5V, 5K - 40K gates » XC4000EX: 0.5 µ m, 5V, 45K - 60K gates » XC4000XL: 0.35 µ m, 3.3V devices, 3K - 180K gates » XC4000XV: 0.25 µ m, 2.5V / 3.3V, 250K - 500K gates – Virtex: New FPGA architecture » 0.25 µ – Spartan: Hi-Volume/Low-Cost solutions (Industry) » 0.5 µ m, 5V, 10K - 40K gates ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 2-6 Xilinx FPGA General Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring Channels IOB IOB IOB IOB CLB CLB CLB CLB IOB Wiring Channels – CMOS Static RAM Technology: programmable on the fly! – All personality elements connected into serial shift register – Shift in string of 1's and 0's on power up
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This note was uploaded on 04/14/2010 for the course ELEC 303 taught by Professor Nil during the Spring '02 term at HKUST.

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lecture3 - ELEC 303 ASIC Design with FPGA Introduction to...

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