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lecture4 - ELEC 303 ASIC Design with FPGA FPGA...

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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-1 FPGA Implementation Design is Technology Independent Design: Enter the design by schematics or VHDL Optimization: Boolean logic optimization Implementation is Technology Independent Technology Mapping » Map the optimized Boolean expressions into logic functions » Chortle-crf Technology Mapper Placement: Place these logic functions into logic blocks Routing: Route wires to connect the logic blocks Implementation: Download the configuration into the FPGA chip • Reference Chapter 2-5, Steven D Brown, Field Programmable gate Arrays, Kluwer Academic Publisher, 1992 ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-2 Xilinx Design Manager Flow
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-3 Technology Mapping: " Directed Acyclic Graph (DAG) The optimized Boolean expression can be represented by a DAG Leaf-DAG: Multi-input and Single-output DAG " Technology Mapping Procedures: Decomposition » Decompose a Boolean network into a forest of leaf-DAG Matching » Match each leaf-DAG with a sub-circuit or library element Covering » Cover the entire Boolean netwrok " DAG example: y = a + bc, z = yd + e 7 nodes a, b, c, d, e, y and z 5 leaf nodes a, b, c, d and e 2 non-leaf nodes y and z 1 root node a + bc yd + e a b c d e y z ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-4 A standard cell library Technology Mapping: Example 1 Example 2 Inv cost = 2 2-NAND cost = 3 2-1-AOI cost = 4 Cost = 13 Cost = 7 Library-Based Technology Mapping (standard cells and gate arrays):
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-5 Look-up Table (LUT) Technology Mapping: " A n-input LUT can have m=2 n input combinations and can implement any of 2 m output functions A n-input LUT is made by a 2 n :1 multiplexer " 2 m is a large number and cannot be maintained in a library for matching purpose 4-input LUT can implement any of 216 = 64k functions 5-input LUT can implement any of 232 = 4G functions " Through input permutation and input/output reverse, 2 m can be reduced to a small number Data Input can go into any input terminal of the LUT The LUT logic block has XOR gate for output reverse Data input from I/O and logic blocks can be reversed " This helps maintain a much smaller logic function library of the n-input LUT for technology mapping ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 4-6 Look-up Table (LUT) Technology Mapping: A 2-input LUT has 2 4 = 16 Boolean functions A B F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 After the input permutation, F4, F5, F12 and F13 were replaced by F2, F3, F10 and F11, respectively. Only 12 functions left B A F2 F3 10 11 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 After the output reverse, 6 more functions (F8, F9, F10, F11, F14 and F15) were removed.
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