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lecture7 - ELEC 303 ASIC Design with FPGA Objectives of...

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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-1 Objectives of Part - II and the Reference Book • Identify features of the Spartan-IIE architecture – Chapter 2 and data sheet • Step through the WebPACK ISE design flow – Chapter 4 and 5 • Apply constraints to optimize performance – Section 5.2 • Use the Report files to analyze Implementation results – Section 5.3 • Create project assignments using Xilinx – Laboratory assignments • Partner with XUP to keep up-to-date with the latest technology – Chapter 7 ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-2 ISE WebPACK Logic Design Tools
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-3 Design Flow XC4000 XC4000 XC4000 3 Design Entry in schematic, ABEL, VHDL, and/or Verilog. Vendors include Synopsys, Aldec (Xilinx Foundation), Mentor, Cadence, Viewlogic, and many others. Implementation includes Placement & Routing and bitstream generation using Xilinx’s M1 Technology. Also, analyze timing, view layout, and more. Download directly to the Xilinx hardware device(s) with unlimited reconfigurations* !! 1 2 ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-4 WebPack Design Flow • The design flow for CPLD & FPGA is almost the same • Three design entry methods – HDL – Schematic – State machines – HDL and Schematic can be mixed • FPGA Implementation – Translate Map into CLB –P lace & Rou te • CPLD Implementation – Translate Fit into Macrocells
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-5 ISE WebPACK provides technology specific optimization for: Device Support •FPGA s –V i r tex i r -E – Virtex-II – Virtex-II Pro – Spartan-II – Spartan-IIE – (Spartan-III) •CP LD s – XC9500 – XC9500XL – XC9500XV – CoolRunner – CoolRunner-II ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-6 HDL code Schematic Netlist Implement Synthesize BIT File Xilinx Design Step • Step1: Design – Design is through project navigator » “Sources in Project” window » “Processes for Current Sources” » “Design Entry” » “Message” – Three design entry methods » HDL(Verilog or VHDL) » Schematic drawings » State machine – Chapter 4 of the reference book • Step 2: Synthesize • Step 3: Implement • Step 4: Configure
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-7 Project Navigator Sources in Project Processes for Current Source Text Editor Message/ Console ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-8 Source Window • The Source window is usually located in the upper-left corner of the Project Navigator • Source window displays – Target device and package – Design files » Displayed hierarchically – Documents and text files – Other tabs: » Snapshot View » Library View
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-9 Processes The Xilinx Design Process steps are listed in the Process for Current Source window Step 1: Design Step 2: Synthesize to create netlist
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lecture7 - ELEC 303 ASIC Design with FPGA Objectives of...

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