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lecture8 - ELEC 303 ASIC Design with FPGA FPGA...

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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-1 Programmable Logic Devices ISE Alliance and Foundation Series Design Software FPGA Configuration • Xilinx Devices – Spartan, Spartan-XL, Spartan-II and Spartan-IIE •ISE D e s i g n F l ow – Design, Synthesis, implementation, configuration • How to configure? – JTAG and ISP? ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-2 Another Script from the Spartan-II Data Sheet
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-3 From Spartan-II Data Sheet ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-4 Summary from the Spartan-II Data Sheet What is ISP? There are four Configuration modes
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-5 Mode Config. Data Format Direction of Synchronizing Clock Use Slave Serial Serial FPGA receives CCLK Processor or CPLD or another FPGA ( in Master mode) controls configuration of slave FPGA Also for configuring multiple slave FPGAs in a daisy chain (2 ND , 3 RD FPGA, etc.). Master Serial Serial FPGA generates CCLK FPGA in Master mode configures itself from a serial PROM. Also, 1 st FPGA (master) in daisy chain controls configuration of slave FPGA(s) in a daisy chain. Slave Parallel Byte FPGA receives CCLK Processor or CPLD controls the fast configuration of slave FPGA. JTAG Serial FPGA receives TCK Make use of existing boundary scan port There are four ways to program a Spartan-II FPGA, The JTAG mode provide a few more ISP options Four Configuration Modes ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-6 What is ISP? Download Cable with Download Cable or Embedded Processor or PROM Download Cable There are three ISP options for different applications
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-7 POF ISE WebPACK or MAX+plus II Programmer BitBlaster, ByteBlaster, or other cable JTAG Chain TMS TCK TDO TDI TMS TCK TDO TDI TMS TCK TDO TDI Any JTAG Device FPGA CPLD Any JTAG Device Use JTAG chain for download (In-System Programmability) IEEE standard 1149.1 Joint Test Action Group (JTAG) interface is a test standard for boundary scan test All ICs should be implemented this feature in their IOB for board-level test Printed Circuit Board (PCB) ISP Flow - ISE WEbPACK or Max+Plus II ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-8 SVF MAX+plus II JTAG Chain SVF2PCF HP- PCF ATE TMS TCK TDO TDI TMS TCK TDO TDI TMS TCK TDO TDI Any JTAG Device FPGA CPLD Any JTAG Device Utility HP Vector Format The Serial Vector Format (SVF) is an industry standard that allows the user to implement JTAG testing and programming Printed Circuit Board (PCB) JTAG chain is normally used for board-level test, Xilinx & Altera just used this interface for downloading the configuration data ISP Flow - Automatic Test Equipment (ATE)
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 7-9 SVF MAX+plus II JTAG Chain Processor TMS TCK TDO TDI TMS TCK TDO TDI TMS TCK TDO TDI Any JTAG Device FPGA CPLD Any JTAG Device
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lecture8 - ELEC 303 ASIC Design with FPGA FPGA...

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