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Lecture5 - ELEC 303 ASIC Design with FPGA FPGA Implementation II Design is Technology Independent Design Optimization Enter the design by

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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-1 FPGA Implementation - II • Design is Technology Independent – Design: Enter the design by schematics or VHDL – Optimization: Boolean logic optimization • Implementation is Technology Independent – Technology Mapping » Map the optimized Boolean expressions into logic functions » Chortle-crf Technology Mapper – Placement: Place these logic functions into logic blocks – Routing: Route wires to connect the logic blocks – Implementation: Download the configuration into the FPGA chip • Reference – Chapter 2-5, Steven D Brown, Field Programmable gate Arrays, Kluwer Academic Publisher, 1992 ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-2 ASIC Development Cycle: • Specifications •D e s i g n •L a y o u t • Implementation •T e s t i n g
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-3 Design Specification – what kind of ASIC ? • Functional Design – high-level functional block diagram •L o g i c Design --- Technology Independent – Boolean network • Circuit Design --- Technology Dependent – circuit schematics Physical Design – layout ? Design Fabrication – wafer fabrication • Package and Testing –AS IC tes t ing A VLSI Design Cycle: ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-4 • Partitioning ( Technology Mapping ) – Group the circuit components into blocks (sub-circuit/standard cell/look-up table) • Floorplan and Placement – Place blocks into the chip according to the floorplan Routing – Complete the interconnections of blocks according to the netlist • Compaction – Compress the layout in all directions to reduce the area Extraction – Extract the circuit from the layout to verify with the original circuit – and do post-layout simulation The Physical Design Cycle:
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ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-5 • Partitioning (Technology Mapping) – In accordance with technology mapping of logic synthesis – major constraints are on the inputs and outputs of the logic blocks •P l a c em e n t – The logic blocks are programmed to resemble the sub-circuit to be mapped or placed • Routing – Complete the interconnections of blocks through the programmable interconnects • Compaction – Cannot be further compacted • Fabrication – Download of the configuration FPGA Physical Design Cycle: ELEC 303 ASIC Design with FPGA Ho-Chi Huang, Lecture Notes, No. 5-6 FPGA Physical Design Example • Technology Mapping – Partitioning the circuit into 4 logic functions, F1, F2, F3 and F4 l a c e n t – F1 to logic block B1 – F2 to logic block B4 – F3 to logic block B7
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This note was uploaded on 04/14/2010 for the course ELEC 303 taught by Professor Nil during the Spring '02 term at HKUST.

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Lecture5 - ELEC 303 ASIC Design with FPGA FPGA Implementation II Design is Technology Independent Design Optimization Enter the design by

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