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Unformatted text preview: University of California, San Diego Department of Electrical and Computer Engineering ECE65, Fall 2009 Lab 5, Logic Gates Note: In this Lab we use CD4007 chip that consists of 3 pairs of complementary n- channel and p-channel MOSFETs. One pair is internally wired as a CMOS inverter. The pin arrangement for the chip is shown below. You need to power the chip by attaching a 5 V supply to pin 14 ( V DD = 5 V) and grounding pin 7. Note that by grounding pin 7, all MOSFET bodies are connected to the lowest voltage in the circuit, 0 V. You can assume V t = 1 . 4 V for your calculations. 2 1 3 14 10 9 8 4 5 6 7 11 12 13 6 10 14 2 7 4 11 12 3 13 8 1 5 9 Experiment 1: BJT Inverter: Circuit Analysis: a) Consider the BJT inverter circuit below. Assume = 200. Compute values of v o for v i = 0, and 5 V. Find the threshold value for v i when BJT would leave the cut-off region ( i.e., the range of v i that input to BJT gate is LOW, V IL ) b) Modify the circuit such that V IL is increased to 1.4 V. PSpice simulation: Set up your circuit with a 2N3904 transistor. Use DC sweep mode to generate a plot of v o as a function of v i for v i ranging from 0 to 5 V. Compare your circuit analysis of part a with the transfer function you have obtained from PSpice....
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- Fall '09