HomeworkThree - to the minimal delay 5 To drive a pair very...

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ECSE 4220 VLSI Design Homework #3 Due: Tue. April 13 in class 2. Given the circuit as shown in Fig. 1. The numbers ‘1’ and ‘32’ associated with the two inverters represent the relative sizes of the inverters. Minimize the path delay from A to B by assigning appropriate size to each gate along the path. State any assumptions you make. 1 32 A B Figure 1: . 3. Given the circuit shown in Fig. 2, denote the delay from A to B, D, E as τ AB , τ AD , and τ AE , respectively. Estimate the ratio τ AB : τ AD : τ AE . R C R C R C R C R C R C R C A B D E Figure 2: . 4. Consider a long wire represented as distributed RC sections. The total wire length is 5mm. To reduce the wire delay, we uniformly insert n buffers along the wire. Suppose r=15Ohms/ μ m and c = 0.25fF/ μ m and the delay of each buffer is 1ns. What is the value of n that could lead
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Unformatted text preview: to the minimal delay? 5. To drive a pair very long wires with signicant amount of inter-line capacitance, we have two different options of inserting inverters as illustrated in Fig.3. 1 (a) which option has the better worst-case signal propagation delay? (b) If one input switches from 1 to 0 and another input switches from 0 to 1, which option delivers the better signal propagation delay? (c) If one input switches from 1 to 0 and another input keeps 1, which option delivers the better signal propagation delay? (d) If one input switches from 1 to 0 and another input switches from 1 to 0, which option delivers the better signal propagation delay? (a) (b) Figure 3: . 2...
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This note was uploaded on 04/15/2010 for the course ECSE 4220 taught by Professor Mcdonald during the Spring '08 term at Rensselaer Polytechnic Institute.

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HomeworkThree - to the minimal delay 5 To drive a pair very...

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