Using Symplicity within Active-HDL

Using Symplicity within Active-HDL - Using Synplicity...

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Using Synplicity within Active-HDL The Makefile supplied with the ML300 tools sets up everything to compile our platform to the Virtex 2 Pro. It is possible, however, to do this all in Active-HDL. While we won’t be setting this up, it can be very beneficial to run Synplicity on our designs in Active-HDL. Doing this will help us make sure we are designing circuits that will synthesize properly. It also avoids the overhead of synthesizing our entire design when we are only working with a single module or small set of modules. The following steps show how to setup Synplicity, analyze a single module, and synthesize an entire design tree, all within Active-HDL. Make sure the synthesis tools are setup for your design in Active-HDL: On the menu bar, click “Design” and choose “Flow Settings…” For “Tool name:” under HDL synthesis , choose “Synplicity Synplify Pro 7.x” Make sure “Location:” is set to the location of synplify_pro.exe, which is
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Using Symplicity within Active-HDL - Using Synplicity...

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