{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

8289 - IHtel PRELMHMW 8289 BUS ARBITER I Provides...

Info icon This preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 2
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 6
Image of page 7

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 8
Image of page 9

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 10
Image of page 11
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: IHtel PRELMHMW 8289 BUS ARBITER I Provides Multl-Master System Bus I Four Operating Modes for Flexible Protocol System Configuration I Synchronizes lAPX 86, 88 Processors I Compatible with intel Bus Standard with MultI-Master Bus MULTIBUSTM I Provldes Simple Interface with 8288 I Provldes System Bus Arbitration for Bus Controller 8089 IOP in Remote Mode The lntel 8289 Bus Arbiter is a 20-pin, 5-volt-only bipolar component for use with medium to large iAPX 86. 88 multi- master/multiprocessing systems. The 8289 provides system bus arbitration for systems with multiple bus masters, such as an 8086 CPU with 8089 IOP in its REMOTE mode, while providing bipolar buffering and drive capability. -s- 1 uumaus’"I 3—1 MULTIBUS COMMAND am anwaou y mrznncs SIGNALS sums ‘ § LOCK CLK PnocEsson m CONTROL RESB ‘mcfl SYSTEM IOB SIGNALS smell-TEE! +5V 20 I Vcc PROCESSOR W 17 l CLK STATUS ' 55:“ 31 6 l 5 Bus 18 l EDEN m Mumaus ‘ ' I FACE 15 l cram: m NTER 14 HEY I Anvnosr conrnou ._. m 13 l m STRAPPING OPTIONS svsam‘EsB svsvsm KEN sIeNALs Figure 2. Pin Diagram Figure 3. Functional Plnout 7-110 8289 Table 1. Pin Description PPRELHMUNARV 80,51,82 Status Input Plns: The status input pins from an 8086, 8085i or 8089 processor. The 8289 decodes these pins to initiate bus re- quest and surrender actions. (See Table 2.) Clock: From the 8284 clock chip and serves to establish when bus arbiter ac- tions are initiated. Lock: A processor generated signal which when activated (low) prevents the arbiter from surrendering the multi—mastersystem bus to any other bus artiter, regardless of i its priority. I Common Request Lock: An active low signal which prevents the arbiter from sur- rendering the multi-master system bus to any other bus arbiter requesting the bus through the CBRG input pin. l Resldent Bus: A strapping option to con- figure the arbiter to operate in systems hav- ing both a multi-master system bus and a Resident Bus. Strapped high. the multi- master system bus is requested or surren- dered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB input is ignored. ANYRQST ..__'__ Any Request: A strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher priority (l.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table 2. if ANY- RQST is strapped high and CBRQ is ac- tivated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 8289 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when Surrender occurs BREQ is driven false (high). l0 Bus: A strapping option which confi- gures the 8289 Arbiter to operate in sys- tems having both an (0 Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders the use of the multi-master system bus as a function of the status line, 15—2, The multi—master sys- tem bus is permitted to be surrendered while the processor is performing IO com- mands and is requested whenever the pro- cessor performs a memory command. Interrupt cycles are assumed as coming fromthe peripheral bus and are treated as an l0 command. Name and Function Symbol J, Type Name and Function Power: +5V supply 1.10%. ATE—ti 0 Address Enable: The output of the 8288 Arbiter to the processor's address latches, to the 8288 Bus Controller and 8284A Clock Generator. m serves to instructthe Bus Controller and address latches when to tri-state their output drivers. System Bus/Resident Bus: An input signal when the arbiter is configured in the SR. Mode (RESB is strapped high) which determines when the multi-master system bus is requested and multi-master system bus surrendering is permitted. The signal is intended to originate from a form of address-mapping circuitry, as a decoder or PROM attached to the resident address bus. Signal transitions and glitches are permitted on this pin from ¢1 of T4 to q) 1 of T2 of the processor cycle. During the period from ¢1 of T2 to 4:1 of T4. only clean transitions are permitted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it. and the multi-master system bus may be requested or surren- dered, depending upon the state of the glitch. The arbiter requests the multi- master system bus In the S.Fl. Mode when the state of the SYSB/RTE§E pin is high and permits the bus to be surrendered when this pin is low. I/O Common Bus Request: An input signal which instructs the arbiter if there are any other arbiters of lower priority requesting the use of the multi-master system bus. The CBRQ pins (open-collector output) of all the 8289 Bus Arbiters which surrender to the multi-master system bus upon re- quest are connected together. The Bus Arbiter running the current trans- fer cycle will not itself pull the CBRQ line low. Any other arbiter connected to the CBRQ line can request the multi-master system bus. The arbiter presently runn__in_g the current transfer cycle drops its BREQ signal and surrenders the bus whenever the proper surrender conditions exist. Strapping CBRQ low and ANYFlQST high allows the multi-master system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST. lNIT l lnltlallze: An active low multi-master sys- tem bus input signal used to reset all the bus arbiters on the multi—master system bus. After initialization, no arbiters have the use of the multi-master system bus. 7-111 AFNAOOBSSC 8289 PREMMHNAE‘W Table 1. Pin Descriptions (Continued) Name and Function Bus Clock: The multi-master system bus clock to which all multi-master system bus interface signals are synchronized. Bu: Request: An active low output signal in the parallel Priority Resolving Scheme which the arbiter activates to request the use of the multi-master system bus. Bus Priority In: The active low signal re- turned to the arbiterto instruct itthat it may acquire the multi-master system bus on the next falling edge of BCLK. BPRN indicates to the arbiter that it is the highest priority requesting arbiter presently on the bus. The loss of BPRN instructs the arbiter that it has lost priority to a higher priority arbiter. FUNCTIONAL DESCRIPTION The 8289 Bus Arbiter operates in conjunction with the 8288 Bus Controller to interface iAPX 86, 88 processors to a multi-master system bus (both the iAPX 86 and iAPX 88 are configured in their m‘ax mode). The processor is un- aware of the arbiter’s existence and issues commands as though it has exclusive use of the system bus. it the pro- cessor does not have the use of the multi-master system bus, the arbiter prevents the Bus Controller (6288), the data transceivers and the address latches from accessing the system bus (e.g. all bus driver outputs are forced into the high impedance state). Since the command sequence was not issued by the 8288, the system bus will appear as ”Not Ready" and the processor will enter wait states. The processor will remain in Wait until the Bus Arbiter ac- quires the use ot the mum-master system bus whereupon the arbiter will allow the bus controller, the data transceiv- ers, and the address latches to access the system. Typi- cally, once the command has been issued and a data transfer has taken place. a transfer acknowledge (XACK) is returned to the processorto indicate “READY” from the accessed slave device. The processor then completes its transfer cycle. Thus'the arbiter serves to multiplex a pro- cessor (or bus master) onto a multl-master system bus and avoid contention problems between bus masters. Arbitration Between Bus Masters In general, higher priority masters obtain the bus when a lower priority master completes its present transfer cycle. Lower priority bus masters obtain the bus when a higher priority master is not accessing the system bus. A strapping option (ANYRQST) ls provided to allow the arbiter to surrender the bus to a lower priority master as though it were a master of higher priority. If there are no other bus masters requesting the bus, the arbiter maln- talns the bus so long as its processor has not entered 7-112 Name and Function Bus Priority Out: An active low output signal used in the serial priority resolving scheme where BPRO is daisy-chained to BPRN of the next lower priority arbiter. Busy: An active low open collector multi-master system bus interface signal used to instruct all the arbiters on the bus when the multi—master system bus is avail- able. When the muiti-master system bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases the BUSYsignal. permitting it to go high and thereby allowing another arbiter to acquire the multi-master system bus. the HALT State. The arbiter will not voluntarily surrender the system bus and has to be forced off by another master’s bus request, the HALT State being the only ex- ception. Additional strapping options permit other modes of operation wherein the multl-master system bus is surrendered or requested under different sets of conditions. Priority Resolving Techniques Since there can be many bus masters on a multi-master system bus, some means of resolving priority between bus masters simultaneously requesting the bus must be provided. The 8289 Bus Arbiter provides several resolv- ing techniques. All the techniques are based on a priori- ty concept that at a given time one bus master will have priority above all the rest. There are provisions for using parallel priority resolving techniques, serial priority resolving techniques, and rotating priority techniques. PARALLEL PRIORITY RESOLVING The parallel priority resolving technique uses a separate bus request line ( for each arbiter on the‘multi- master system bus, see Figure 4. Each BFiEQ line enters into a priority encoder which generates the binary ad- dress of the highest priority BFiEQ line which is active. The binary address is decoded by a decoder to select the corresponding BPRN (Bus Priority In) line to be returned to the highest priority requesting arbiter. The arbiter receiving priority (BPRN true) then allows its associated bus master onto the multl-master system bus as soon as it becomes available (i.e., the bus is no longer busy). When one bus arbiter gains priority over another arbiter it cannot immediately seize the bus, it must wait until the present bus transaction is complete. AFN-008390 Upon completing its transaction the present bus occu- pant recognizes that it no lonflhas priority and sur- renders the bus by releasing BUSY. BUSY is an active low “OR" tied signal line which goes to every bus arbiter on the system bus. When BUSY goes Inactive (high), the arbiter which presently has bus priority (BPRN true) then -US ARBITER PRELIMINARY seizes the bus and pulls BUSY low to keep other arbiters off of the bus. See waveform timing diagram, Figure 5. Note that all multl-master system bus transactions are synchronized to the bus clock (BCLK). This allows the parallel prlority resolving circuitry or any other prlorlty resolving scheme employed to settle. 74148 74138 PRIORITY 3 TO B ENCODER DECODER BUS ARBITER _ 2 BUS ARBITER _ 3 aus ARBITER 4 . ca Figure 4. Parallel Priority Resolving Technique 0 LOWER PRIORITY BUS ARBITER RELEASES BUSY. o HIGHER PRIORITY BUS ARBITER REQUESTS THE MULTI-MASTER SYSTEM BUS. O ATTAINS PRIORITY 0 HIGHER PRIORITY BUS ARBITER THEN ACOUIRES THE BUS AND PULLS BUSY DOWN. Figure 5. Higher Priority Arbiter obtaining the Bus from a Lower Prlorlty Arbiter 7-1 13 AFN-008390 SERIAL PRIORITY RESOLVING The serial prlonty resolving technique eliminates the need for the priority encoder-decoder arrangement by daisy-chaining the bus arbiters together, connecting the higher priority bus arbiter’s BPRO (Bus Priority Out) out- put to the BPRN of the next lower priority. See Figure 6. BUS ARBITER 1 BUS ARBITER 2 BUS ARBITER 3 BUS ARBITER a THE NUMBER OF ARIITERS THAT MAY BE DAISYvCHAINED TOGETNER IN THE SERIAL PRIORITY RESOLVINO SCHEME IS A FUNCTION OF BCLK AND THE PROPA- GATION DELAY FROM ARBITER TO ARBITER. NORMALLY, AT 10 MN: ONLY 3 ARBI- TER MAY BE DAISV-CHAINED. Figure 6. Serial Priority Resolving ROTATING PRIORITY RESOLVING The rotating prlorlty resolving technique is similar to that of the parallel priority resolving technlque except that priority is dynamically re-assigned. The priority en- coder Is replaced by a more complex circuit which ro- tates prlorlty between requesting arbiters thus allowing each arbiter an equal chance to use the mum-master system bus, over time. llI’Vhich Priority Resolving Technique To se There are advantages and disadvantages for each of the techniques described above. The rotating priority resolving technique requires substantial external logic to implement while the serial technique uses no exter- nal logic but can accommodate only a limited number of bus arbiters before the daisy-chain propagation delay exceeds the multi-master’s system bus clock (BCLK). The parallel prlorlty resolving technique is in general a good compromise between the other two techniques. It allows for many arbiters to be present on the bus while not requiring too much logic to implement. ‘In some system configurations It is possible for a non-l/O Processor to have access to more than one MultI-Master System Bus, see 8289 Application Note. 7-114 8289 PRELIMINARY 8289 MODES OF OPERATION There are two types of processors in the iAPX 86 family. An Input/Output processor (the 8089 IOP) and the iAPX 86/10, 88/10 CPUs. Consequently, there are two basic operating modes in the 8289 bus arbiter. One, the IOB (l/O Peripheral Bus) mode, permits the processor access to both an l/O Peripheral Bus and a multi-master system bus. The sec- ond, the RESB (Resident Bus mode), permits the pro- cessor to communicate over both a Resident Bus and a multi-master system bus. An l/O Peripheral Bus is a bus where all devices on that bus, including memory, are treated as l/O devices and are addressed by l/O com- mands. All memory commands are directed to another bus, the multi-master system bus. A Resident Bus can issue both memory and l/O commands, but it is a distinct and separate bus from the multi-master system bus. The distinction is that the Resident Bus has only one master, providing full availability and being dedicated to that one master. The IO—B strapping option configures the 8289 Bus Ar- biter into the l—O_B mode and the strapping option RESB configures it into the RESB mode. It might be noted at this point that if both strapping options are strapped false, the arbiter interfaces the processor to a multi- master system bus only (see Figure 7). With both op- tions strapped true, the arbiter interfaces the processor to a multi-master system bus, a Resident Bus, and an I/O Bus. In the EB mode, the processor communicates and con trols a host of peripherals over the Peripheral Bus. When the IIO Processor needs to communicate with system memory, it does so over the system memory bus. Figure B shows a possible I/O Processor system configuration. The iAPX 86 and iAPX 88 processors can communicate with a Resident Bus and a rnulti-master system bus. Two bus controllers and only one Bus Arbiter would be needed in such a configuration as shown in Figure 9. in such a system configuration the processor would have access to memory and peripherals of both busses. Memory map- ping techniques are appliecl to select which bus is to be accessed. The SYSB/RESB input on the arbiter serves to instruct the arbiter as to whether or not the system bus is to be accessed. The signal connected to SYSB/RESB‘» also enables or disables commands from one of the bus controllers. A summary of the modes that the 8289 has, along with its response to its status lines inputs, is summarized in Table 2. AFN-008390 inter 8289 PRELMHNAW Table 2. Summary of 8289 Modes, Requesting and Relinquishing the Multl-Master System Bus Status Lines From IOB Mode RESB (Mode) Only IOB Mods RESB Mode 8086 or 8088 or 8089 Only IOB = High RESB = High IOB = Low RESB = ngh |/O COMMANDS MEM COMMANDS NOTES: 1. X: Multi-Master System Bus Is allowed to be Surrendered. 2. r = Multi-Master System Bus is Requested. Pin MultI-Master System Bus Strapping Requested' ' I Single Bus W: High Whenever the processor’s \ Made Surrondorod‘ t Multl-Master Mode RESB: Low status lines go active HLT+ Tl ' CBRQ+ HPBRQ (SYSB/R'E'S‘B = Low + Tl) . CBRQ + HLT+ HPBRQ (l/O Status + TI) - CBRQ + HLT+ HPBHQ ((I/O Status Commands)+ IOB = Low (Memory Command) 0 _ IOB Mode'FlESB Mode . — . ass/FEB- Low» - cane mass = ngh (SYSB/RESB: ngh) + HPBRQf + HLT 63‘: High SYSB/FiES'B: High . RESB Mode Only Hess: High ACTIVE STATUS fix: Low RESB = Low IOB Mode Only Memory Commands NOTES: 'LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower prlorlty arbiter. "Except for HALT and Passive or IDLE Status. THP_B_IRQ, Higher priority Bus request or BPRN = 1. 1. IOB Active Low. 2. RESB Active High. 3. +ls read as “OR” and . angflD.” 4. TI = Processor idle Status 52, s1.fi= 111 5. HLT= Processor Halt Status F2, a 3'6 = 011 7-1 1 5 AFN-008396 I 8289 PRELHMUNAW XACK MULTI-MAS'ER SYSTEM BUS MULTI~MASTER ODNYROL BUS I239 BUS ARBITEI CLK A Vcc was CPU AmADIs 53 sums (Sims—Isa) azna "mums“, sz AIbAw BUS SVSYEM coumousa COMMAND CLK aus MuLnMASTER ALE .0. svsvsu nus DEN DT/fi cs MULTI-MASTER ADDRESS Fnocssson LAYCH SVS‘I’EM LOCAL aus amt ADDRESS am ““5 (2 OH 3) _< _XCVR m c: uni MULTl-MASVER TRANSCEIVER SYSTEM IZWIZIY 9 DATA {2) BUS XACK (no nus} 7,—__< XACK MULTI~MASTER SVSTEM nus ~ MULYI MASVER comnoL ___._ BUS id's ANYROSTRESB - 3239 Bus ARDIYER READY c LK 5059 IOP ADo-Ams 5’ A“ ”9 5—2 sums (515755) seen us DDNYROLLER MuLn MASTER svSvEM COMMAND HUS CLK .05 mm * Mqu~MAsTER VCC SVSTEM 5st AL: no “”5 PDEN DEN Io , COMMAND Bus ' 5TB as STE ADDRESS ADDRESS MULYI MASYER m . lATCH ”“9“ SVSTEM ADDRESS 818W _ BUS am: am Anvil-.55 .282 (2 0R 3) XCVR HUS a on a) DISABLE TRANSCEIVER azuluzai (2) YRANSCEIVER MuLn MASTER azuslnfl ’7 SVSTEM (2) if, DAYA aus Figure 8. Typlcal Medlum Complexlty IOB System 7-1 16 AFN—003390 RESUDENT BUS XACK RESIDENT IUS KEN - In“ CLOCK —- Inn RDVI READV ELK READV CLK 5'03? am CFU ADO-A015. A1fl-AII 8289 srATus RESIDENY COMMAND nus PROM 0R DECOBER Anna Bus LATCN ”maze: RESIDENY ADDRESS < NESIDENY DAYA nus (2 OR ID TRANSCEIVER 325410257 (2) ADDR LATCH 5232mm (2 on 3) "IA NscEIVER azsalazu {2) ‘IV ADDING ANOYHER em ARBITER AND CONNECTING ITs AEN Y0 YHE an: VINOSE KEN IS PRESENVLV GROUNDED, THE PROCESSOR COULD HAVE ACCESS TU “NO MULYl-MASTER BUSES, PRELUMUNARY xAcK MULTI‘MABYER SVBYEM I“: MULYI‘MASTER SVSYEM BUS CONTROL MULTIMASYER SVSYEM COMMAND Bus MuLTI-MAerR svsTEM ADDRESS BUS MuLTI-MASTEN sverM DATA Ills Flgure 9. 8289 Bus Arbiter Shown In System-Resident Bus Conflguratlon 7-117 MULYI-MASTER svs‘rEM aus AFNOOBaSC inter 8289 PRELUMUNARV ABSOLUTE MAX|MUM RATINGS‘ *NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional opera- Temperature Under Bias ................ 0°C to 70°C tion of the device at these or any other conditions aibove Storage Temperature ............. — 65°C to + 150°C those indicated in the operational sections of this specifi- All Output and Supply Voltages ........ — 0.5V to + 7V cation is not implied. Exposure to absolute maximum All Input Voltages .................. — 1.0V to + 5.5V rating conditions for extended periods may affect device Power Dlsslpatlon ......................... 1.5 Watt reliability. D.C. CHARACTERISTICS (TA = 0°C to 70°C, vCC = +5v 110%) Symbol ‘ Parameter Vc Input Clamp Voltage _ Input Forward Current Test Condition VCC = 4.50V, Io: — 5 mA Vac = 5.50V, VF = 0.45V ...
View Full Document

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern