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Unformatted text preview: E © INTEL CORPORATION 1996, 1997 April 1997 Order Number: 290550-002 n Bridge Between the PCI Bus and ISA Bus n PCI and ISA Master/Slave Interface PCI from 25–33 MHz ISA from 7.5–8.33 MHz 5 ISA Slots n Fast IDE Interface Supports PIO and Bus Master IDE Supports up to Mode 4 Timings Transfer Rates to 22 MB/Sec 8 x 32-Bit Buffer for Bus Master IDE PCI Burst Transfers Separate Master/Slave IDE Mode Support (PIIX3) n Plug-n-Play Port for Motherboard Devices 2 Steerable DMA Channels (PIIX Only) Fast DMA with 4-Byte Buffer (PIIX Only) 2 Steerable Interrupts Lines on the PIIX and 1 Steerable Interrupt Line on the PIIX3 1 Programmable Chip Select n Steerable PCI Interrupts for PCI Device Plug- n-Play n PCI Specification Revision 2.1 Compliant (PIIX3) n Functionality of One 82C54 Timer System Timer; Refresh Request; Speaker Tone Output n Two 82C59 Interrupt Controller Functions 14 Interrupts Supported Independently Programmable for Edge/Level Sensitivity n Enhanced DMA Functions Two 8237 DMA Controllers Fast Type F DMA Compatible DMA Transfers 7 Independently Programmable Channels n X-Bus Peripheral Support Chip Select Decode Controls Lower X-Bus Data Byte Transceiver n I/O Advanced Programmable Interrupt Controller (IOAPIC) Support (PIIX3) n Universal Serial Bus (USB) Host Controller (PIIX3) Compatible with Universal Host Controller Interface (UHCI) Contains Root Hub with 2 USB Ports n System Power Management (Intel SMM Support) Programmable System Management Interrupt (SMI)—Hardware Events, Software Events, EXTSMI# Programmable CPU Clock Control (STPCLK#) Fast On/Off Mode n Non-Maskable Interrupts (NMI) PCI System Error Reporting n NAND Tree for Board-Level ATE Testing n 208-Pin QFP The 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerators are multi-function PCI devices implementing a PCI-to-ISA bridge function and an PCI IDE function. In addition, the PIIX3 implements a Universal Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3 integrates many common I/O functions found in ISA-based PC systems—a seven-channel DMA controller, two 82C59 interrupt controllers, an 8254 timer/counter, and power management support. In addition to compatible transfers, each DMA channel supports type F transfers. Chip select decoding is provided for BIOS, real time clock, and keyboard controller. Edge/Level interrupts and interrupt steering are supported for PCI plug and play compatibility. The PIIX/PIIX3 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. The PIIX/PIIX3 provides motherboard plug and play compatibility. PIIX implements two steerable DMA channels (including type F transfers) and up to two steerable interrupt lines. PIIX3 implements one steerable interrupt line. The interrupt lines can be routed to any of the available ISA interrupts. Both PIIX/PIIX3 implement a programmable chip select.PIIX/PIIX3 implement a programmable chip select....
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- Spring '10
- Central processing unit, PCI Express, Interrupt, Computer buses