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Unformatted text preview: * Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. December 1995 COPYRIGHT ' INTEL CORPORATION, 1995 Order Number: 231630-011 Intel386 TM DX MICROPROCESSOR 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Y Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers Y Very Large Address Space — 4 Gigabyte Physical — 64 Terabyte Virtual — 4 Gigabyte Maximum Segment Size Y Integrated Memory Management Unit — Virtual Memory Support — Optional On-Chip Paging — 4 Levels of Protection — Fully Compatible with 80286 Y Object Code Compatible with All 8086 Family Microprocessors Y Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System Y Hardware Debugging Support Y Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus Bandwidth Y Numerics Support via Intel387 TM DX Math Coprocessor Y Complete System Development Support — Software: C, PL/M, Assembler System Generation Tools — Debuggers: PSCOPE, ICE TM-386 Y High Speed CHMOS IV Technology Y 132 Pin Grid Array Package Y 132 Pin Plastic Quad Flat Package (See Packaging Specification, Order 231369) The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications and operating systems such as MS-DOS and Windows. The 32-bit registers and data paths support 32-bit addresses and data types. The processor addresses up to four gigabytes of physical memory and 64 terabytes (2 ** 46) of virtual memory. The integrated memory management and protection architecture includes address translation registers, multitasking hardware and a protection mechanism to support operating systems. Instruc- tion pipelining, on-chip address translation, ensure short average instruction execution times and maximum system throughput. The Intel386 DX CPU offers new testability and debugging features. Testability features include a self-test and direct access to the page translation cache. Four new breakpoint registers provide breakpoint traps on code execution or data accesses, for powerful debugging of even ROM-based systems....
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This note was uploaded on 04/18/2010 for the course ARCH Arch 101 taught by Professor Edwardhoe during the Spring '10 term at 카이스트, 한국과학기술원.
- Spring '10