CS433: Computer Systems Organization Fall 2009
Homework 3
Assigned: Oct/1
Due in class Oct/13
Total points: 54 for undergraduate students, 62 for graduate students.
Instructions:
Please write your name, NetID and an alias on your homework submissions for posting grades
(If you don’t want your grades posted, then don’t write an alias). We will use this alias
throughout the semester. Homeworks are due in class on the date posted.
Problem 1: Loop Unrolling [18 points]
In this problem, we will use the pipeline shown in Figure A.31 on page A.50 of your book. Its
characteristics are:
•
If unspecified, its properties are like those in the MIPS pipeline.
•
There is 1 integer functional unit, taking 1 cycle to perform integer addition (including
effective address calculation for loads/stores), subtraction, logic operations and branch
operations.
•
There is 1 FP/integer multiplier, taking 8 cycles to perform multiplication. It is pipelined.
•
There is 1 FP adder, taking 3 cycles to perform FP additions and subtractions. It is
pipelined.
•
There is 1 FP/integer divider, taking 24 cycles. It is NOT pipelined.
•
There is full forwarding and bypassing, including forwarding from the end of an FU to
the MEM stage for stores.
•
Loads and stores complete in one cycle. That is, they spend one cycle in the MEM stage
after the effective address calculation.
•
There are as many registers, both FP and integer, as you need.
•
There is one branch delay slot.
•
While the hardware has full forwarding and bypassing, it is the responsibility of the
compiler to schedule such that the operands of each instruction are available when
needed by each instruction.
Loop:
L.D
F4, 0 (R1)
MUL.D
F8, F4, F0
L.D
F6, 0 (R2)
ADD.D
F10, F6, F2
ADD.D
F12, F8, F10
S.D
F12, 0 (R3)
DADDUI
R1, R1, 8
DADDUI
R2, R2, 8
DADDUI
R3, R3, 8
DSUB
R5, R4, R1
BNEZ
R5, Loop