09 Adders (Part I)

09 Adders (Part I) - EE115C Digital Electronic Circuits...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 9: Adders – Part I
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One-Bit Full Adder The Binary Adder Full dd ut A B adder Sum C out C in SA B C i ⊕⊕ = A = BC i ABC i i i +++ C o AB BC i AC i ++ = EE115C 2
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Multi-Bit Adders : Example A 0 B 0 A 1 B 1 A 2 B 2 A 3 B 3 FA FA FA FA C i ,0 C o ,0 ( = C i ,1 ) C o ,1 C o ,2 C o ,3 S 0 S 1 S 2 S 3 , t adder = ( N 1) t carry + t sum Goals very low t adder small adder (layout) area 3 adder cells should be identical, preferably EE115C
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Full Adder Design ± Choice of architecture ipple adder Ripple adder Carry bypass Carry select Carry look-ahead ± Choice of circuits Static CMOS irror Adder Mirror Adder Transmission-Gate Adders Manchester-Carry Chain Later, in “Adders–Part II” 4 EE115C
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Adder Architectural Improvements 5 EE115C
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Inversion Property A B AB C C i FA C C FA S o o i S 6 EE115C
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Minimize Critical Path by Reducing Inverting Stages A 3 Even cell Odd cell A 0 B 0 A 1 B 1 A 2 B 2 B 3 FA FA FA FA C i ,0 C o ,0 C o ,1 C o ,3 C o ,2 S 0 S 1 S 2 S 3 xploit Inversion Property 7 Exploit Inversion Property EE115C
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Full Adder – Another Look… AB Full adder C out C in Sum Define 3 new variables which ONLY depend on A and B Delete = A B Generate (G) = AB Propagate (P) = A B ote: ternate definition for 8 Propagate (P) = A + B Note: alternate definition for P EE115C
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S and C out as a Function of P, G, D, C in ropagate (P) = A Delete = A B Generate (G) = AB Propagate (P) A B Can also derive expressions for S and C ut based on D and P out 9 EE115C
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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09 Adders (Part I) - EE115C Digital Electronic Circuits...

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