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00 Course Outline - EE115C Winter 2010 Digital Electronic...

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EE115C – Winter 2010 igital Electronic Circuits Digital Electronic Circuits Boelter Hall Rm #02444
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Personnel ± Instructor Sudhakar Pamarti 6731F Boelter Hall, (310) 825 2657, spamarti@ee.ucla.edu Office Hours: MW 10:00am – 11:00am ± TA Amarnath Kasibahtla ± Reader BD TBD EE115C – Winter 2010 2
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Digital Integrated Circuits ± Basics Transistor behavior and fabrication technology ± Simple Static CMOS Logic Gate (Circuit) Design Delay, power analyses, transistor sizing, and layout terconnect (Wires) ± Interconnect (Wires) R and C ± Combinatorial Logic Block Design Chain of logic gates Delay analysis, sizing; logical effort equential Logic Block Design ± Sequential Logic Block Design Latches, flip-flops, timing analysis ± Design and simulation experience 3 Cadence software, generic 90nm CMOS process EE115C – Winter 2010
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Class Organization ± 6 homework assignments Due one week from date of assignment, at the beginning of class
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00 Course Outline - EE115C Winter 2010 Digital Electronic...

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