03a CMOS Inverter

03a CMOS Inverter - EE115C Winter 2010 Digital Electronic...

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EE115C – Winter 2010 igital Electronic Circuits Digital Electronic Circuits Lecture 3: Static CMOS – Inverter
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Mapping Between Analog Signals and Digital Levels Volts V IH V OH “1” V DD Nominal Value Minimum Allowable Value Undefined Region 0.5V DD V IL Maximum Allowable Value “0” V OH GND Nominal Value 2 EE115C
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Noise Margins V H V D Volts V H V D Lowest Voltage Ckt. #2 still treats oise Margin High V IH OH DD 5V V IH OH DD as “1” Noise Margin High, NM H =V OH –V IH V IL 0.5V DD V IL 0.5V DD ighest Voltage oise Margin High V OH GND V OH GND Highest Voltage Ckt. #2 still treats as “0” Noise Margin High, NM H =V IL OL Digital Ckt. #1 Digital Ckt. #2 3 EE115C
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Simplest Digital Electronic Circuit – Inverter V DD V in V DD OFF ON, Triode V in V out V out GND C L Input 1 0 1 utput Output 0 1 0 ON, Triode FF 4 EE115C OFF
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Inverter – Voltage Transfer Characteristic (VTC) V DD NMOS off PMOS res NMOS sat 1.0 V out V in V out NMOS sat MOS t PMOS res 0.6 0.8 C L NMOS res PMOS sat NMOS res PMOS sat 0.2 0.4 V in 0.2 0.4 0.6 0.8 1.0 PMOS off 5 EE115C
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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03a CMOS Inverter - EE115C Winter 2010 Digital Electronic...

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