06 CMOS Gate Sizing

06 CMOS Gate Sizing - EE115C Digital Electronic Circuits...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 6: CMOS Logic Gate Sizing
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Transistor Sizing ± Match worst cases to inverter pull-up and pull-down sistances R p R p R p resistances A B B R p t 22 4 C L B R n A C int 2 4 A R n C int A R n B R n C L 2 1 1 EE115C 2
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Sizing of a Complex CMOS Gate: Example A B 4 8 D C 4 8 OUT = D + A • (B + C) A 2 D BC 1 22 3 EE115C
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Fan-In and Fan-Out Definitions N M an- ut an 4 Fan out N Fan-in M EE115C
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Fan-In Considerations D C B A istributed RC model B A C L C 3 Distributed RC model (Elmore delay) D C C 2 C 1 t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) Propagation delay deteriorates rapidly as a function of fan-in – adratically the worst case 5 quadratically in the worst case. EE115C
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t p as a Function of Fan-In 1250 quadratic NAND2 ps) 750 1000 HL t p (p 500 t pHL t p 0 250 linear t pLH fan-in 2468 1 0 1 2 1 4 1 6 6 ± Gates with fan-in > 4 should be avoided EE115C
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t p as a Function of Fan-Out 5 t p NAND2 t p NOR2 4 ± All gates have the same drive current (norm.) t p INV 2 3 ± Slope is a
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06 CMOS Gate Sizing - EE115C Digital Electronic Circuits...

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