07 Sizing of Chain of Gates

07 Sizing of Chain of Gates - EE115C Digital Electronic...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 7: Chain of Gates: Delay and Sizing
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Logical Effort Formulation Basic concept: ± elay = R ate ad + C elf = R ate ad + R ate lf Actual definition; Delay R gate (C load C self ) R gate C load R gate C self ± Normalized delay d = Delay/ τ = (R gate C load + R gate C self )/ R inv C inv ormalized to the delay of a FO inverter (no self load) Simplified definition Normalized to the delay of a FO-1 inverter (no self load) Simplified case: R gate = R inv , self load C C + N N effort delay, parasitic delay, inv f p d CC =+ d is a measure that is independent of process, voltage, temp If R gate R inv , we can still use this formulation, but is more complicated EE115C 2
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Logical, Electrical, and Parasitic Efforts self load C C + N N effort delay, parasitic delay, inv fp d CC =+ _ gate in load load v inv gate in C f C == × _ logical effort, electrical effort, inv g h ±²³ 3 EE115C
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Calculating Logical Effort (1/2) DEF: Logical effort is the ratio of the input capacitance to the input capacitance of an inverter delivering the same output current OR2: NOR2: C in = 5 LE = 5/3 verter: NAND2: Inverter: C in = 3 LE = 1 (def) C in = 4 LE = 4/3 Reference EE115C
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Calculating Logical Effort (2/2) Procedure: 1. Choose an input 2. Calculate total MOS transistor width driven by that input (nMOS + pMOS) 3. Consider a reference inverter with the same drive strength Make sure rise and fall delays are same i.e. β ≅ μ n / μ p e.g. 2.5 Calculate total device width of the inverter (nMOS + pMOS) 4. Divide Step 2 by Step 4 to determine g 5 EE115C
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Calculating Parasitic Delay (1/2) DEF: Parasitic delay is the ratio of intrinsic capacitance at the output and intrinsic capacitance at the output of an equivalent inverter OR2: NOR2: C int = 6 P = 2 verter: NAND2: Inverter: C int = 3 P = 1 (def) C int = 6 Reference EE115C
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Calculating Parasitic Delay (2/2)
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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07 Sizing of Chain of Gates - EE115C Digital Electronic...

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