10b IC Layout and Design Rules

10b IC Layout and Design Rules - EE115C Digital Electronic...

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EE115C Digital Electronic Circuits Lecture 10b: Layout and Design Rules
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EE115C 2 CMOS Inverter: Side and Top Views Side View (Cross-section) Top View Courtesy: CMOS VLSI Design, Weste …
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3 CMOS Inverter: Mask View Top View Courtesy: CMOS VLSI Design, Weste … n-Well poly Silicon n+ diffusion p+ diffusion contacts Metal 1 EE115C
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4 IC Fabrication and Layout Layout A collection of mask views or mask drawings Designer prepares them based on schematics Usually with the help of software Magic, Cadence Virtuoso, etc. Often automated in the case of digital circuits Fabrication Process A collection of physical and chemical processes Photolithography – “writing with light in stone” Foundry builds die according to layout drawings E.g., IBM, Taiwan Semiconductor Manufacturing Company (TSMC) … Incredible quality control EE115C
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5 Design Rules EE115C
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6 Design Rules: Terminology (1/2) EE115C
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7 Design Rules: Terminology (2/2) EE115C
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8 Layout Layer Basics: Transistors EE115C
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9 Interpreting Design Rules: n-well Design Rules Example (Definitions) Design Rule Tables (N-Well Example) EE115C
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10 Interpreting Deign Rules: Nwell Design Rules (Physical View) EE115C
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11 Transistor Layers Conceptual view Cadence representation EE115C
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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10b IC Layout and Design Rules - EE115C Digital Electronic...

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