11b Dynamic Logic

11b Dynamic Logic - EE115C Digital Electronic Circuits...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 11b: Dynamic Logic
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Dynamic Gate M CLK CLK M n off In 1 Out C L Out on 1 AB+C In 2 PDN In 3 A B C M e CLK CLK M e o phase operation off on Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) Out CLK A B C CLK =+ + EE115C 2
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Conditions on Output ± Once the output of a dynamic gate is discharged, it cannot be charged again until the next pre-charge ca ot be c a ged aga u t t e e t p e cag e operation. ± Inputs to the gate can make at most one transition during evaluation. ± Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C 3 EE115C
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Properties of Dynamic Gates : Advantages ± Logic function is implemented by the PDN only number of transistors is N + 2 (vs. 2N for static CMOS) () ± Full swing outputs (V OL = GND and V OH = V DD ) ± Faster switching speeds duced load capacitance due to wer input pacitance (C reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) 4 EE115C
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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11b Dynamic Logic - EE115C Digital Electronic Circuits...

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