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12 13 Latches, Flip-Flops, Timing

12 13 Latches, Flip-Flops, Timing - EE115C Winter 2010...

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EE115C – Winter 2010 igital Electronic Circuits Digital Electronic Circuits Lectures 12 & 13: Latches, Flip-Flops and Timing
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Uses : Finite State Machines COMBINATIONAL LOGIC Outputs Inputs Registers Next state Current State LK QD CLK EE115C 2
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Uses : Pipelining EG RE REG log a CLK Out log a CLK LK LK LK Out CLK CLK b CLK CLK CLK CLK b f ipelined Reference Pipelined 3 EE115C
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Latch versus Register (Flip-Flop) ± Register: edge-triggered ores data when ± Latch: level-sensitive ock is low old mode stores data when clock rises clock is low – hold mode clock is high – transparent D lk Q D Clk Q Clk Clk Clk D D 4 Q Q EE115C
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Latches Positive Latch Negative Latch In Out D G Q In Out D G Q clk CLK clk CLK In Out In Out Out stable Out follows In Out stable Out follows In 5 EE115C
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Latch Circuits 6 EE115C
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Mux-Based Latches Negative latch ransparent when CLK= 0) Positive latch ransparent when CLK= 1) (transparent when CLK= 0) (transparent when CLK= 1) 1 Q 0 Q 0 D LK 1 D CLK CLK QC l k Q C l k D = ⋅+ Q Clk Q Clk D =⋅ +⋅ 7 EE115C
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Mux-Based Latch LK CLK CLK Q M Q CLK M CLK NMOS only Non-overlapping clocks 8 EE115C
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Positive Feedback During Latch Hold Operation D Q Q LK V o1 V i2 CLK V V i1 A o2 V i2 =V o1 When CLK = Low C B 9 V o2 EE115C
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Meta-Stability A o1 A V i2 5 C C B B ain should be larger than 1 in the transition region d V i1 5 V o2 V 5 V o2 10 Gain should be larger than 1 in the transition region EE115C
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Transmission Gate Mux Based Latch CLK Q CLK D CLK Protection from input noise 11 EE115C
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Alternative Latch Structure SRQ ! Q emory S !Q 0 0 Q !Q memory 1010 s e t set 0 1 0 1 reset 1100 disallowed R Q D !Q transparent mode Q clock 12 clock hold mode EE115C
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Dynamic Latch Circuits CLK D Q CLK Charge stored on this capacitor when CLK is High 13 EE115C
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Other Dynamic Latches: Clocked CMOS (C 2 MOS) D D Clk Q Q Clk Clk Clk removed Transmission gate latch with gate isolation (dynamic) C 2 MOS latch (dynamic) 14 EE115C
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Static Vs Dynamic Latches CLK Dynamic (charge-based) Static D Q CLK Q CLK CLK D CLK This node is NOT driven when CLK is High; can lose charge to leakage, noise etc.; problems similar to that of dynamic circuitry. 15 EE115C
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Pseudo-Static Latch ynamic seudo atic CLK CLK Dynamic Pseudo-static D D D Q CLK CLK 16 EE115C
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A Popular Mux-Gate Based Latch Clk Clk 1 Clk D S M Clk Q 1 Clk 1 Protection from input noise 17 EE115C
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Characterizing Latches t Clk DQ D Q t setup t hold l DATA STABLE C DATA t D Q t C Q STABLE Negative Latch 18 EE115C
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Setup-Hold Time Illustrations Circuit before clock arrival (Setup-1 case) N
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12 13 Latches, Flip-Flops, Timing - EE115C Winter 2010...

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