14 Wires (Interconnect)

14 Wires (Interconnect) - EE115C Digital Electronic...

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EE115C igital Electronic Circuits Digital Electronic Circuits Lecture 14: Wires (Interconnect)
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The Wire transmitters receivers schematics physical EE115C 2
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Modern Interconnect 3 EE115C
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Wire Models All-inclusive model Capacitance-only 4 EE115C
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Impact of Interconnect Parasitics ± Interconnect parasitics reduce reliability affect performance and power consumption ± Classes of parasitics apacitive Capacitive Resistive Inductive 5 EE115C
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Capacitance: The Parallel Plate Model Current flow L W lectrical eld lines ielectric H Electrical-field lines Dielectric t di Substrate WL t c di di int ε = 6 EE115C
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Dielectric Permittivity 7 EE115C
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Fringing Capacitance Capacitance er unit length per unit length W - H/2 H (a) + 8 (b) fringe pp EE115C
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Interwire Capacitance fringing parallel 9 EE115C
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Impact of Interwire Capacitance 10 From: L. Shaper, D. Amey, “Improved Electrical Performance Required for Future MOS Packaging,” IEEE Trans. Components, Hybrids, and Manufacturing Technology, Sep 1983, pp. 282-289.
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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14 Wires (Interconnect) - EE115C Digital Electronic...

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