Homework 01

Homework 01 - EE115C,Winter2010,HW#1(due1/21/2010) Note:...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 115C, Winter 2010, HW #1 (due 1/21/2010) Note: The Cadence assignments i.e. problems #1 and #4 are due on 1/28/2009 to give you more time with Cadence. Problem 1: Using Cadence Spectre, generate the family of I-V curves for a NMOS transistor with the following parameters: W/L = 240nm/100nm Sweep V DS from 0V to 1V in 50mV increments Sweep V GS = 0.05, 0.1, 0.15, 0.2, 0.25, 0.3V, 0.35, 0.4, 0.7V, 1.0V V SB = 0V, 0.4V The online Tutorial #1 (from EEWeb > Online Laboratory) has detailed instructions on how to do this. Use the 90nm model as instructed in Tutorial 1, use section NN in the transistor model. (a) Plot all I-V curves on one graph and label bias conditions for V GS and V SB . (b) Plot all I-V curves on one graph with a logarithmic y-axis and label bias conditions for V GS and V SB . (c) Determine the values of the parameters, V T0 , V DSAT , γ , λ , and k n ’, from the family of I-V curves. You may assume that 2 Φ F = –0.6V. (10 + 10 + 10 = 30 points) Problem 2: (Voltage Transfer Characteristic) Figure 1 shows the voltage transfer characteristic of a special inverter. The inverter has
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

Page1 / 2

Homework 01 - EE115C,Winter2010,HW#1(due1/21/2010) Note:...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online