Homework 02

Homework 02 - EE 115C, Winter 2010, HW #2 (due 1/28/2010)...

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EE 115C, Winter 2010, HW #2 (due 1/28/2010) Problem 1: (Same as Problem 7 from Hw #1; moved into Hw#2 as noted in class) Consider the circuit in Figure 1. Calculate the total equivalent capacitance on nodes X and Y as they dis- charge from V DD to V DD /2. The length of each diffusion region for all transistors is L s = 0.1μm. Use the capacitance para- meters posted on the class web-site in the “Handouts” section for your calculations. (20 points) Problem 2: CMOS Inverter Delay Calculation and Design (a) Calculate the t pLH , t pHL , and t P for a standard CMOS inverter with minimum length devices (L = 90nm) and NMOS width is 90nm and the PMOS width is 270nm. Use the resistance and capa- citance parameters tables posted on the class web-site in the “Handouts” section for your calcula- tions. (b) Choose the size of the PMOS transistor so as to minimize the propagation delay, t P . Calculate the t pLH , t pHL , and t p for the chosen size. (10 + 20 = 30 points)
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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Homework 02 - EE 115C, Winter 2010, HW #2 (due 1/28/2010)...

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