Homework 03

# Homework 03 - EE115C,Winter2010,HW#3(due Problem 1 Static...

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EE 115C, Winter 2010, HW #3 (due 2/4/2010) Problem 1: Static CMOS Gate Delay and Sizing Consider the circuit shown in Figure 2. This is called a “mirror adder” circuit; it is a good start- ing point for the adder circuits in your project. It computes the sum of A, B, and Cin, and gene- rates two output bits, S, and Cout. It includes two complex static CMOS gates (Gate #1 and Gate #2 in the figure) that respectively generate Cout and S which are subsequently inverted to gen- erate Cout and S. Sizing: Choose the sizes of the transistors of both Gate #1 and Gate #2 such that their worst case pull-up and pull-down resistances are the same as that of a reference inverter of size (W/L) nMOS = 120nm/100nm and (W/L) pMOS = 240nm/100nm. Logical Effort: Determine the logical effort of input labeled “Cin” for both Gate #1 and Gate #2. Assume that C GN ’ = C GP ’ = C G ’. (20 + 20 = 40 points) Problem 2: Multi-Gate Delay Analysis Using Logical Effort (35 points) Calculate the delay at the output node, n4, of the chain of gates shown in Figure 2 for a H

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## This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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Homework 03 - EE115C,Winter2010,HW#3(due Problem 1 Static...

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