Homework 03

Homework 03 - EE115C,Winter2010,HW#3(due2/4/2010) Problem...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 115C, Winter 2010, HW #3 (due 2/4/2010) Problem 1: Static CMOS Gate Delay and Sizing Consider the circuit shown in Figure 2. This is called a “mirror adder” circuit; it is a good start- ing point for the adder circuits in your project. It computes the sum of A, B, and Cin, and gene- rates two output bits, S, and Cout. It includes two complex static CMOS gates (Gate #1 and Gate #2 in the figure) that respectively generate Cout and S which are subsequently inverted to gen- erate Cout and S. Sizing: Choose the sizes of the transistors of both Gate #1 and Gate #2 such that their worst case pull-up and pull-down resistances are the same as that of a reference inverter of size (W/L) nMOS = 120nm/100nm and (W/L) pMOS = 240nm/100nm. Logical Effort: Determine the logical effort of input labeled “Cin” for both Gate #1 and Gate #2. Assume that C GN ’ = C GP ’ = C G ’. (20 + 20 = 40 points) Problem 2: Multi-Gate Delay Analysis Using Logical Effort (35 points) Calculate the delay at the output node, n4, of the chain of gates shown in Figure 2 for a H
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 3

Homework 03 - EE115C,Winter2010,HW#3(due2/4/2010) Problem...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online