Homework 05

Homework 05 - EE 115C, Winter 2010, HW #5 (due 2/25/2010)...

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EE 115C, Winter 2010, HW #5 (due 2/25/2010) Problem 1: (Dynamic Logic and Adder) Draw the schematic of a dynamic logic circuit that generates the look-ahead Carry out (inverted) for a group of three bits. Assume that the propo- gate and generate signals are available to you. (20 points) Problem 1: (Dynamic Logic) Please refer to a type of dynamic logic circuit shown in Figure 1(a). The signal CLK is a periodic square wave of time period T. a) Does the circuit evaluate during CLK = 1 or during CLK = 0? Explain. b) Determine the logical function Y = Y(A,B,C,D) realized during the evaluate phase. c) Determine the input pattern that causes the worst charge sharing between the output capacit- ance and the capacitances on the internal nodes. Assume that each of the internal nodes of the circuit has capacitance of 1 fF to ground and the output Y has a capacitance of 10 fF to ground. d) Calculate the final voltage on the output node after the worst case charge sharing identified in part (c) occurs. Assume that V DD = 1.0 V and that the transistors have the following proper-
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Homework 05 - EE 115C, Winter 2010, HW #5 (due 2/25/2010)...

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