Project Schematic submission details

Project Schematic submission details - What you should...

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What you should submit? 1. Group member names and UIDs. 2. Average power of your design. The method to measure power is described in next section. 3. Speed of your system (i.e., maximum clock frequency) at which your system can generate correct Fibonacci sequence (F0 to F16) AND compare against threshold value to correctly generate the signal OUT. Clock frequency is the value of Freq that you set in Analog Design Environment, for which your Fibonacci generation and Threshold comparison are fully functional. 4. Snapshot of the output bits of F of a full set of Fibonacci sequence (F0 to F16). Show a snapshot of transient signals of all bits of F and clock. Label each bit and clock signal. 5. Location of your Library, Cell and State file for our verification of the above three. Specify your project’ s complete path so that we can verify your design for its functionality as well as speed and power numbers that you report. For this purpose we need the complete path of your library that has your design, the cell name of your design, the path to the state file which we can just load and run. Please set all the variables and analyses required to run your setup before saving the state file that you provide us. We should be able to just load the state file and run in order to verify your design. Most importantly, you should keep a back-up of your design (library, cell and state file) as well as give only READ and EXECUTE permissions (chmod 755 -R *) to
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This note was uploaded on 04/18/2010 for the course EE 115C taught by Professor N/a during the Spring '10 term at UCLA.

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Project Schematic submission details - What you should...

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