Textbook - Lecture Correspondence

Textbook - Lecture Correspondence - EE115C,S09: TEXTBOOK J...

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EE 115C, S’09 : Lecture – Text Book Correspondence T EXTBOOK J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Edition, Prentice Hall, NJ, 2002. C ORRESPONDENCE Topics Page Numbers in Text Book Introduction 3-10, 52-54 MOS Long Channel 87-93 MOS Short Channel 94-103 Velocity Saturation Unified Model Threshold Variations 114-115 Fabrication & Design Rules Fabrication 35-50 Design Rules 198, color plates between 10,11 MOS as a Switch Equivalent Resistance 104-106 Capacitances 107-112 Logic Styles Pass Transistor Logic 269-272, 277-283 Ratio, pseudo-nMOS Logic 264-265 Static CMOS : construction 235-240 CMOS Delay, Simple Propagation delay definitions, t pHL , t pLH 27-28 Inverter Delay 199-202 o Calculation o Sizing for t pHL = t pLH Static CMOS Delay, Complex Input Pattern Dependence 242-246 Elmore Delay 153-154 Sizing only class notes, 250 Multi-Stage Static CMOS Delay and Sizing Logical Effort 251-256, inside back cover Inverter Chain Sizing 205-210, class notes
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