final 07 solution

final 07 solution - Solution: decrease registers, increase...

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1) Problem: Too many capacity misses in the data cache Solution: Increase size of cache Drawback: larger latency, power Problem: Too many control hazards Solution: dynamic branch prediction Drawback: more power consumption Problem: Our carry lookahead adder is too slow Solution: use hierarchical adder, pipelining Drawback: increase complexity Problem: We want to be able to use a larger immediate field in the MIPS ISA
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Unformatted text preview: Solution: decrease registers, increase instruction size, decrease OP code Drawback: resource spilling, complexity of coding will grow, decrease instruction Problem: The execution time of our CPU with a single-cycle datapath is too high Solution: multicycle, pipelining Drawback: complexity (more hardware such as more latches), increase CPI...
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This note was uploaded on 04/18/2010 for the course CS 151B taught by Professor N/a during the Spring '10 term at UCLA.

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