Hw2 - done on slide 10 of lecture 5. Problem 3. In the...

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Problem 1. Using the diagrams on slides 20 and 23 from lecture 4, what is the maximal latency to drive out the final Carry-Out and all Sum bits for the specific 16- bit hierarchical carry lookahead adder we discussed in class? Assume that for any logic gate (and, or, xor) with a fan-in of k (i.e. number of inputs), the delay of that gate is k/2 times T (rounded down to the nearest whole number). So a gate with fan- in 2 or 3 would have delay T, and fan-in of 4 or 5 would have delay 2T, etc. Print out those two slides and show your work rather than just giving the final answer (which should be in terms of T). Problem 2. Use Booth's Algorithm to multiply 1010 by 0110. Show your work as was
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Unformatted text preview: done on slide 10 of lecture 5. Problem 3. In the worst case, Booth's algorithm can actually perform more operations (adds and shifts) than the multiply algorithm of slide 3 of lecture 5. What is that worst case? Problem 4. To avoid the worst case in problem 3, we will try a new version of Booth's algorithm - one that looks at three bits of the multiplier at a time rather than just two. Can you formulate a table like the one in slide 9 that handles a three bit Booth's algorithm? HINT - consider the current bit, the bit to the right, and then the bit to the right of that....
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This note was uploaded on 04/18/2010 for the course CS 151B taught by Professor N/a during the Spring '10 term at UCLA.

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