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hw2_sol - Problem 1 Using the diagrams on slides 20 and 23...

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Unformatted text preview: Problem 1. Using the diagrams on slides 20 and 23 from lecture 4, what is the maximal latency to drive out the final Carry-Out and all Sum bits for a 16-bit hierarchical carry lookahead adder? Assume that for any logic gate (and, or, xor) with a fan-in of k (i.e. number of inputs), the delay of that gate is k/2 times T (rounded down to the nearest whole number). So a gate with fan-in 2 or 3 would have delay T, and fan—in of 4 or 5 would have delay 2T, etc. Print out those two slides and show your work rather than just giving the final answer (which should be in terms of T). G = A and B ( = T ) P = A xor B ( H H From Slide 20, we get that G (alpha, beta, gamma) = GO.P1.P2.P3 + Gl.PO.P1 + G2.PO.P1 + G3 { {fix w, T T T T T T T T T T T T + 2T(.) T + T(.) T + T(.) T 3T + 2T(+) G(alpha, beta, gamma) = 5T xT(.l+) —> indicates that there is delay ’x’ for that operation Similarly for P (alpha, beta, gamma) = PO.P1.P2.P3 we get, T + 2T(-) P(alpha, beta, gamma) = 3T From slide 23, // C12 = Gy + GB.Py + Goc.PB.Py + CO.Poc.PB.Py 5T 5T T 5T 3T 3T 0 3T 3T 3T 5T 5T+T(.) 5T+T(.) T+2T(.) 6T + 2T(+) C12 = 8T Using the formula for C3 from Slide 20 with Cin = C12, C15 = G2 + G1.P2 + GO.P1.P2 + Cin.PO.P1.P2 T T T T T T 8T T T T T T+T(.) T+T(.) 8T+2T(.) lOT + 2T(+) C15 12T 815 A15 xor B15 xor C15 OT OT 12T 815 = 12T + T(Xor) = l3T Extend formula from slide 23 to get, C16 = G8 + G728 + GB.P7.P6 + Goc.PB.Py.P8 + CO.Poc.PB.Py.P8 We get C16 = 9T Maximal Latency = 13T (Sum) Problem 2. Use Booth's Algorithm to multiply 1010 by 0110. Show your work as was done on slide 12 of lecture 5. Operation Multiplicand Product / Next 0. Initial 1010 0000;0110 0 00 —> NOOP 1a. 0000 0p11 0 ‘ Shift 1b. + 0110 0000 10 —> Sub \ 0110 4011 2a 0011 0001 1 Shift 2b 0011 OOLl 1 11 —> NOOP 3a 0001 100% 1 Shift 3b + 1010 000p 01 —> Add gfiawiXxfifl£m%~ 1011 100:0[ . 4a I j>1101 1100i0 Shift 4b 1101 1100 p Done Problem 3. In the worst case, Booth's algorithm can actually perform more operations (adds and shifts) than the multiply algorithm of slide 5 of lecture 5. What is that worst case? Worst case for Booth’s algorithm is a sequence 1010 Problem 4. To avoid the worst case in problem 3, we will try a new version of Booth's algorithm - one that looks at three bits of the multiplier at a time rather than just two. Can you formulate a table like the one in slide 10 that handles a three bit Booth‘s algorithm? HINT - consider the current bit, the bit to the right, and then the bit to the right of that. —— nothing Mddle of a run of Os. do nothin I {)6 :noth§ng add 1) 10 : sub, 03 : add {3*}: -> —b + 2b = ’0 add 2b 11 : nothing, {)1 :add 13*? -> +2b suhb Dlzadd 10:5ub2 * b ->b—2b=-b Sub b 7 f} 1 sub 2b 90 : nothing, If) : sub b*2 -> -2b 1 I nothing Middle of a run of 15. Do nothing After each operation product is Shifted twice. An adding or subuactmg b after a shift to right is similar to shifting b to left and doing add or subtraction. So we can use 2*!) (shifted b) when it is the second operation. Rf '03: 5 : 0 was :7 it"? + Hum A44 haw-meme A -, a ’ 1,. W (“00 O $M.Hr13 U“ +093 0 MA ‘0‘: we 0’. j: (3} i? a , L, .r Del») Vi}: (“Ad/W) + 00! o co: 2- A3 a=010101 =21 b=000110 -> 223:001100 -b=111010 -2b=1}0100 b=6 000000 01010} O (010: addb) 00030 000110 010101 0 (shift mithmefic twice) 000001 100101 0 (010: addb} 000110 000131100101 1 (Shifitwica) 000001 111001 0 (010: add b) 000110 00013.1 11100} 0 (Shift mice) 000001 H1110 0 product : 0130001 111110 =126 There are 3 operafiens, where there are 6 operations in {moth 2 algorithm (for each 01 and 10 there is one add or subtract) ...
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