hw5 - 2. Caching In on the TLB (20 points): Consider the...

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3 2. Caching In on the TLB (20 points) : Consider the data cache for a processor that uses byte addressed memory. The cache is a 4KB 2-way set associative cache with an 8 byte block size that uses LRU replacement within a set. Stores on our processor use write around and write through. Our cache is virtually indexed and physically tagged. We use an 8-way set associative 1KB TLB, and our virtual memory uses 16KB pages. We have 2 48 B of virtual memory and 2 30 B of physical memory. There are no extra bits required in each page table entry aside from the bits needed for the physical page number. Calculate the hit rate of the cache and TLB on the given stream of virtual byte addresses. Each address is shown in binary and in decimal. The type of instruction that accessed the data cache is also shown – load or store. Note that there are 6 unique byte addresses here – and that the sequence of six addresses is repeated to make 12 total addresses below. Mark whether the cache and TLB has a “hit” or “miss” for each address – i.e. whether or not the desired memory address is found in the cache and whether or not the desired translation is in the TLB. For the addresses – assume that “. ..” means all leading 0’s.
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This note was uploaded on 04/18/2010 for the course CS 151B taught by Professor N/a during the Spring '10 term at UCLA.

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hw5 - 2. Caching In on the TLB (20 points): Consider the...

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