Lecture 06 The Processor

Lecture 06 The Processor - Chapter 4 The Processor 4.1...

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Chapter 4 The Processor
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Chapter 4 — The Processor — 2 Introduction ± CPU performance factors ± Instruction count ± CPI and Cycle time ± We will examine three MIPS implementations ± A single-cycle implementation ± A multi-cycle implementation ± A pipelined version ± Simple subset, shows most aspects ± Memory reference: lw , sw ± Arithmetic/logical: add , sub , and , or , slt ± Control transfer: beq , j §4.1 Introduction
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Chapter 4 — The Processor — 3 Instruction Execution ± PC instruction memory, fetch instruction ± Register numbers register file, read registers ± Depending on instruction class ± Use ALU to calculate ± Arithmetic result ± Memory address for load/store ± Branch target address ± Access data memory for load/store ± PC target address or PC + 4
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Chapter 4 — The Processor — 4 CPU Overview
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Chapter 4 — The Processor — 5 Multiplexers ± Can’t just join wires together ± Use multiplexers
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Chapter 4 — The Processor — 6 Control
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Chapter 4 — The Processor — 7 Logic Design Basics §4.2 Logic Design Conventions ± Information encoded in binary ± Low voltage = 0, High voltage = 1 ± One wire per bit ± Multi-bit data encoded on multi-wire buses ± Combinational element ± Operate on data ± Output is a function of input ± State (sequential) elements ± Store information
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Chapter 4 — The Processor — 8 Combinational Elements ± AND-gate ± A B Y I0 I1 Y M u x S ± Multiplexer ± Y = S ? I1 : I0 A B Y + A B Y ALU F ± Adder ± Y = A + B ± Arithmetic/Logic Unit ± Y = F(A, B)
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This note was uploaded on 04/18/2010 for the course CS 151B taught by Professor N/a during the Spring '10 term at UCLA.

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Lecture 06 The Processor - Chapter 4 The Processor 4.1...

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