Lecture 07 Multicycle

Lecture 07 Multicycle - Reinman 8-1 CS M151B / EE M116C...

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Unformatted text preview: Reinman 8-1 CS M151B / EE M116C Computer Systems Architecture Multicycle Some notes adopted from Dean Tullsen and Larry Carter at UCSD Reinman 8-2 Single Cycle Implementation PC Instruction memory R ead address Instruction [31 0] Instruction [20 16] Instruction [25 21] Add Instruction [5 0] M emtoReg ALU Op M emW rite R egW rite M emR ead Branch R eg Dst ALU Src Instruction [31 26] 4 16 32 Instruction [15 0] M u x 1 Control Add ALU result M u x 1 Registers W rite reg ister W rite data R ead da ta 1 R ead da ta 2 R ead reg ister 1 R ead reg ister 2 Sig n extend M u x 1 ALU result Zero PCS rc Data mem ory W rite data R ead data M u x 1 Instruction [15 11] ALU control Shift left 2 ALU Address Reinman 8-3 Single-cycle designs need a cycle time that can fit the instruction with the longest delay Solution: break execution into smaller tasks each task takes a cycle different instructions require different numbers of cycles Need fewer logic blocks One ALU versus ALU plus 2 adders? One unified (instruction + data) memory port? CPI will increase, but cycle time should drop Why Go Multicycle? Reinman 8-4 Steps in the Multicycle Implementation Five execution steps (some instructions use fewer) IF: Instruction Fetch ID: Instruction Decode (& register fetch & add PC+immed) EX: Execute Mem: Memory access WB: Write-Back into registers Reinman 8-5 Single Cycle Datapath Partitioning MemtoReg MemRead MemWrite ALUOp ALUSrc RegDst PC Instruction memory Read address Instruction [31 0] Instruction [20 16] Instruction [25 21] Add Instruction [5 0] RegWrite 4 16 32 Instruction [15 0] Registers Write register Write data Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend ALU result Zero Data memory Address Read data M u x 1 M u x 1 M u x 1 M u x 1 Instruction [15 11] ALU control Shift left 2 PCSrc ALU Add ALU result WB Mem EX ID IF Goal is to balance work done in each cycle - minimize cycle time! Reinman 8-6 We Need More State Elements Extra registers needed when signal is computed in one clock cycle and used in another inputs to the functional block that produces this signal can change before the signal is written into a state element PC Memory Address Instruction or data Data Instruction register Registers Register # Data Register # Register # ALU Memory data register A B ALUOut Reinman 8-7 Multicycle Datapath Shift left 2 MemtoReg IorD MemRead MemWrite PC Memory MemData Write data M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15 11] M u x 1 M u x 1 4 ALUOp ALUSrcB RegDst RegWrite Instruction [15 0] Instruction [5 0] Sign extend 32 16 Instruction [25 21] Instruction [20 16] Instruction [15 0] Instruction register 1 M u x 3 2 ALU control M u x 1 ALU result ALU ALUSrcA Zero A B ALUOut IRWrite Address Memory data register Reinman 8-8 Step 1: Fetch IR = Mem[PC] PC = PC + 4 (NOTE: the PC may change later) Fetch the instruction from memory Compute the address of the next sequential instruction Reinman 8-9...
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Lecture 07 Multicycle - Reinman 8-1 CS M151B / EE M116C...

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