Lecture 09 Hazards

Lecture 09 Hazards - CS M151B / EE M116C Computer Systems...

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Reinman 10-1 CS M151B / EE M116C Computer Systems Architecture Hazards Some notes adopted from Dean Tullsen and Larry Carter at UCSD
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Reinman 10-2 Pipelined Implementation Datapath Instruction Fetch Instruction Decode/ Register Fetch Execute/ Address Calculation Memory Access Write Back Instruction memory Address 4 32 0 Add Add result Shift left 2 IF/ID EX/MEM MEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Data memory Address
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Reinman 10-3 Data Hazards • When a result is needed in the pipeline before it is available, a “data hazard” occurs. IM Reg ALU DM Reg IM Reg DM IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 sub $2 , $1, $3 and $12, $2 , $5 or $13, $6, $2 add $14, $2 , $2 sw $15, 100( $2 ) R2 Available R2 Available R2 Needed R2 Needed
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Reinman 10-4 Dealing With Data Hazards • Register file bypass eliminates one hazard. – First half-cycle of cycle 5: register 2 written – Second half-cycle: new value is read IM Reg ALU DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 sub $2 , $1, $3 and $12, $6 , $5 or $13, $6, $8 add $14, $2 , $2 R2 Available R2 Available
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Reinman 10-5 Dealing with Data Hazards • In Software – insert independent instructions (or no-ops) • In Hardware – insert bubbles (i.e. stall the pipeline) – data forwarding
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Reinman 10-6 Dealing with Data Hazards in Software IM Reg ALU DM Reg IM Reg DM Reg IM Reg DM Reg IM Reg DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 sub $2 , $1, $3 nop add $12, $2, $5 nop Insert enough no-ops (or other instructions that don’t use register 2) so that data hazard doesn’t occur,
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Reinman 10-7 Code Scheduling to Avoid Stalls • Reorder code to avoid use of load result in the next instruction • C code for A = B + E; C = B + F; lw $t1, 0($t0) lw $t2 , 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4 , 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall lw $t1, 0($t0) lw $t2 , 4($t0) lw $t4 , 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles 13 cycles
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Reinman 10-8 Where are No-ops needed? • sub $2, $1,$3 • and $4, $2,$5 • or $8, $2,$6 • add $9, $4,$2 • slt $1, $6,$7 • Are no-ops really necessary?
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Reinman 10-9 Handling Data Hazards in Hardware • Stall the pipeline sub $2 , $1, $3 add $12, $2 , $5 or $13, $6, $2 add $14, $2 , $2 IM Reg DM Reg IM Reg DM IM Reg DM Reg IM Reg DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 Bubble Bubble
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Reinman 10-10 Handling Data Hazards in Hardware sub $2, $1, $3 add $12, $3, $5 or $13, $6, $2 add $14, $12, $2 IM Reg DM Reg IM Reg DM IM Reg DM Reg IM Reg DM Reg CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 Bubble Bubble sw $14, 100 ($2) Reg IM Reg DM CC9 CC10 CC11 Bubble
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Reinman 10-11 Pipeline Stalls • To insure proper pipeline execution in light of register dependences, we must:
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This note was uploaded on 04/18/2010 for the course CS 151B taught by Professor N/a during the Spring '10 term at UCLA.

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Lecture 09 Hazards - CS M151B / EE M116C Computer Systems...

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